set_dont_touch  rnumdec
set_dont_touch  regfile_decode
set_dont_touch  vctalucinmxmu
set_dont_touch  vctaluctlmx0mu
set_dont_touch  vctrndvlu1anac
set_dont_touch  vctrndvlu1mxac
set_dont_touch  vctrndvlu2aoac
set_dont_touch	vctacup0slmxac
set_dont_touch	vctacup1slmxac
set_dont_touch	vctclpsgnmuwb


set_input_delay 4 -clock clk {reset_l};

set_input_delay 13 -clock clk {su_instvld_rd};
set_input_delay 12 -clock clk {vdp_vs_sign_rd};
set_input_delay 11 -clock clk {vct_aluprectl_rd};
set_input_delay 11 -clock clk {vct_absop_rd};

set_input_delay 2 -clock clk {vct_instvld_mu};
set_input_delay 8 -clock clk {vct_addcop_mu};
set_input_delay 8 -clock clk {vct_subcop_mu};
set_input_delay 2 -clock clk {vct_addop_mu};
set_input_delay 2 -clock clk {vct_subop_mu};
set_input_delay 8 -clock clk {vct_vs_sgnmu_mu};
set_input_delay 8 -clock clk {vct_vt_sgnmu_mu};
set_input_delay 8 -clock clk {vct_stltop_mu};
set_input_delay 8 -clock clk {vct_steqop_mu};
set_input_delay 8 -clock clk {vct_stneop_mu};
set_input_delay 8 -clock clk {vct_stgeop_mu};
set_input_delay 2 -clock clk {vct_stchop_mu};
set_input_delay 2 -clock clk {vct_stclop_mu};
set_input_delay 2 -clock clk {vct_stchrop_mu};
set_input_delay 2 -clock clk {vct_stcrop_mu};
set_input_delay 2 -clock clk {vct_substclop_mu};

set_input_delay 2 -clock clk {vct_absop_mu};
set_input_delay 8 -clock clk {vct_rndop_mu};
set_input_delay 8 -clock clk {vct_rndpop_mu};
set_input_delay 8 -clock clk {vct_rndnop_mu};
set_input_delay 8 -clock clk {vct_mulqop_mu};
set_input_delay 8 -clock clk {vct_mulfop_mu};
set_input_delay 8 -clock clk {vct_muluop_mu};
set_input_delay 2 -clock clk {vct_vseqone_mu};
set_input_delay 2 -clock clk {vct_aluprectl_mu};
set_input_delay 2 -clock clk {vct_aluprecin_rd};
set_input_delay 8 -clock clk {vct_cryoutld_mu};
set_input_delay 8 -clock clk {vct_cmpcdld_mu};
set_input_delay 8 -clock clk {vct_cmpcdadld_mu};

set_input_delay 8 -clock clk {vdp_vs_zero_mu};
set_input_delay 8 -clock clk {vdp_vt_zero_mu};
set_input_delay 2.5 -clock clk {vdp_vt_sign_mu};
set_input_delay 10 -clock clk {vdp_aluovr_mu};
set_input_delay 10 -clock clk {vdp_aluco_mu};
set_input_delay 11.5 -clock clk {vdp_aluzero_mu};
set_input_delay 11.5 -clock clk {vdp_aluone_mu};

set_input_delay 8 -clock clk {vct_prsmlwrsl_mu};


set_input_delay 2 -clock clk {vct_instvld_ac};
set_input_delay 2 -clock clk {vct_prcslwasl_ac};
set_input_delay 2 -clock clk {vct_prcslwbsl_ac};
set_input_delay 2 -clock clk {vct_prcsupasl_ac};
set_input_delay 2 -clock clk {vct_prcsupbsl_ac};
set_input_delay 2 -clock clk {vct_prcsupcen_ac};

set_input_delay 2 -clock clk {vct_stchop_ac};
set_input_delay 2 -clock clk {vct_stclop_ac};
set_input_delay 2 -clock clk {vct_stnclrdop_ac};
set_input_delay 2 -clock clk {vct_stclrdop_ac};
set_input_delay 2 -clock clk {vct_multtypop_ac};
set_input_delay 2 -clock clk {vct_macqop_ac};
set_input_delay 2 -clock clk {vct_mudlop_ac};
set_input_delay 2 -clock clk {vct_madlop_ac};
set_input_delay 2 -clock clk {vct_mulfop_ac};
set_input_delay 2 -clock clk {vct_muluop_ac};
set_input_delay 2 -clock clk {vct_rndpop_ac};
set_input_delay 2 -clock clk {vct_rndnop_ac};

set_input_delay 2 -clock clk {vct_absop_ac};
set_input_delay 2 -clock clk {vct_vseqone_ac};
set_input_delay 8 -clock clk {vdp_addlwco_ac};
set_input_delay 8 -clock clk {vdp_addlwov_ac};
set_input_delay 8 -clock clk {vdp_csupco_ac};
set_input_delay 12 -clock clk {vdp_addupco_ac};

set_input_delay 4 -clock clk {vmu_co_clal_ac};
set_input_delay 4 -clock clk {vmu_co_clah_ac};

set_input_delay 8 -clock clk {vct_praclwsl_ac};
set_input_delay 8 -clock clk {vct_pracmisl_ac};
set_input_delay 8 -clock clk {vct_pracupsl_ac};

set_input_delay 2 -clock clk {vct_multactyp_ac};
set_input_delay 2 -clock clk {vct_multincop_ac};


set_input_delay 8 -clock clk {su_wrcmpcd_wb};
set_input_delay 8 -clock clk {su_wrcmpcdad_wb};
set_input_delay 8 -clock clk {su_wrcryout_wb};
set_input_delay 12 -clock clk {su_datainlo_wb};
set_input_delay 12 -clock clk {su_datainhi_wb};

set_input_delay 3 -clock clk {vdp_accbit15_wb, vdp_accbit21_wb};
set_input_delay 3 -clock clk {vdp_accbit31_wb, vdp_accbit47_wb};

set_input_delay 4 -clock clk {vdp_acchizero_wb, vdp_acchione_wb, vdp_accmizero_wb};

set_input_delay 1.5 -clock clk {vct_acchighsl_wb};
set_input_delay 1.5 -clock clk {vct_accmidsl_wb};
set_input_delay 1.5 -clock clk {vct_acclowsl_wb};
set_input_delay 1.5 -clock clk {vct_accshftsl_wb};
set_input_delay 1.5 -clock clk {vct_divrsltsl_wb};
set_input_delay 1.5 -clock clk {vct_clpsgn31_wb};
set_input_delay 1.5 -clock clk {vct_clpsgn16_wb};
set_input_delay 1.5 -clock clk {vct_clpsgn32_wb};
set_input_delay 1.5 -clock clk {vct_clpuns31_wb};
set_input_delay 1.5 -clock clk {vct_adscl16op_wb};



set_output_delay -max 10.5 -clock clk {vct_aluctl_mu};
set_output_delay -max 10.5 -clock clk {vct_alucin_mu};
set_output_delay -max 6.0 -clock clk {vct_compvt_mu};
set_output_delay -max 4.0 -clock clk {vct_smlwrsl_mu};

set_output_delay -max 12.0 -clock clk {vct_cryout_ac};
set_output_delay -max 12.0 -clock clk {vct_opdneql_ac};
set_output_delay -max 12.0 -clock clk {vct_cmpcdlo_ac};
set_output_delay -max 12.0 -clock clk {vct_cmpcdhi_ac};
set_output_delay -max 12.0 -clock clk {vct_cmpcdad_ac};

set_output_delay -max 8.0 -clock clk {vct_rndvlu_ac};
set_output_delay -max 10.0 -clock clk {vct_cslwasl_ac};
set_output_delay -max 10.0 -clock clk {vct_cslwbsl_ac};
set_output_delay -max 9.0 -clock clk {vct_addlwci_ac};
set_output_delay -max 9.0 -clock clk {vct_csupasl_ac};
set_output_delay -max 9.0 -clock clk {vct_csupbsl_ac};
set_output_delay -max 9.0 -clock clk {vct_csupcen_ac};
set_output_delay -max 9.0 -clock clk {vct_incrdwn_ac};
set_output_delay -max 9.0 -clock clk {vct_incrci_ac};
set_output_delay -max 7.0 -clock clk {vct_incrmxsl_ac};

set_output_delay -max 2.0 -clock clk	{vct_aclwsl_ac};
set_output_delay -max 2.0 -clock clk	{vct_acmisl_ac};
set_output_delay -max 1.0 -clock clk	{vct_acupsl_ac};

set_output_delay -max 6.0 -clock clk	{vct_rsltsl_wb};
set_output_delay -max 6.0 -clock clk	{vct_clprslt_wb};


set_input_delay 8.3 -clock clk {su_xp_rnum_rd[0]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[1]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[2]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[3]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[4]};

set_input_delay 9 -clock clk {su_st_rnum_rd[0]};
set_input_delay 9 -clock clk {su_st_rnum_rd[1]};
set_input_delay 9 -clock clk {su_st_rnum_rd[2]};
set_input_delay 9 -clock clk {su_st_rnum_rd[3]};
set_input_delay 9 -clock clk {su_st_rnum_rd[4]};

set_input_delay 9 -clock clk {su_ld_rnum_ac[0]};
set_input_delay 9 -clock clk {su_ld_rnum_ac[1]};
set_input_delay 9 -clock clk {su_ld_rnum_ac[2]};
set_input_delay 9 -clock clk {su_ld_rnum_ac[3]};
set_input_delay 9 -clock clk {su_ld_rnum_ac[4]};

set_input_delay 2.0 -clock clk {su_vd_addr_wb};
set_input_delay 2.0 -clock clk {su_wbv_wr_en_wb};
set_input_delay 2.0 -clock clk {su_bwe_wb};
set_input_delay 8 -clock clk {su_xposeop_rdac};
set_drive 0 {slice};
set_input_delay 0.0 -clock clk {slice};
set_input_delay 2.0 -clock clk {wb_div_elem};
set_input_delay 2.0 -clock clk {wb_div_type};

set_output_delay -max 5 -clock clk {vct_rfadrt_hi_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_hi_wb}
set_output_delay -max 5 -clock clk {vct_rfadrt_lo_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_lo_wb}
set_output_delay -max 2 -clock clk {vct_rfadrt_st_rd}
set_output_delay -max 2 -clock clk {vct_rfadrf_st_rd}
set_output_delay -max 5 -clock clk {vct_rfadrt_vd_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_vd_wb}