vuctlsl.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 15.0 -waveform {0 7.5}; \
set_input_delay 13.0 -clock clk all_inputs(); \
set_input_delay 7.0 clk ; \
set_clock_skew -uncertainty 1 clk; \
fix_hold clk; \
dont_touch_network clk; \
set_output_delay -max 13.0 -clock clk all_outputs(); \
set_driving_cell -cell in01d1 all_inputs(); \
set_driving_cell -cell in01d2 vdp_acchizero_wb; \
set_driving_cell -cell in01d2 vdp_acchione_wb; \
set_driving_cell -cell in01d2 vdp_vt_sign_mu; \
set_drive 0 {clk}; \
set_load 1.0 all_outputs();"
/* setup the search path for includes */
search_path = search_path + "../src"
/* read the verilog sources */
read -f verilog ../src/vuctlsl.v
/*
*read -f verilog ../../rsp/src/rsp_lden32_f.v
*read -f verilog ../../rsp/src/rsp_lden32_t.v
*/
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
read -f edif rnumdec.edf
current_design = vuctlsl
set_default_operating_conditions
set_default_timing_constraints
max_area 1500
set_max_fanout 16 current_design;
set_max_fanout 8 all_inputs();
set_max_fanout 16000 clk;
set_max_transition 2.0 current_design;
include vuctlsl.con
link
check_design > vuctlsl.lint
current_design = vuctlsl
compile -map_effort high -ungroup_all -boundary_optimization
report -reference > report/vuctlsl1.ref
report_area > report/vuctlsl1.area
report_net > report/vuctlsl1.net
report_constraint -all_violators > report/vuctlsl1.violators
report_timing -path full -delay max -max_paths 10 > report/vuctlsl1.full.paths
report_clock > report/vuctlsl1.clock
write -f edif -o vuctlsl1.edf -hier vuctlsl
compile -map_effort high -ungroup_all -boundary_optimization
report -reference > report/vuctlsl2.ref
report_area > report/vuctlsl2.area
report_net > report/vuctlsl2.net
report_constraint -all_violators > report/vuctlsl2.violators
report_timing -path full -delay max -max_paths 10 > report/vuctlsl2.full.paths
report_clock > report/vuctlsl2.clock
write -f edif -o vuctlsl2.edf -hier vuctlsl
/*
remove_attribute find(reference, "rnumdec") dont_touch
*/
remove_attribute find(cell, "vctalucinmxmu") dont_touch
remove_attribute find(cell, "vctaluctlmx0mu") dont_touch
remove_attribute find(cell, "vctrndvlu1anac") dont_touch
remove_attribute find(cell, "vctrndvlu1mxac") dont_touch
remove_attribute find(cell, "vctrndvlu2aoac") dont_touch
remove_attribute find(cell, "vctacup0slmxac") dont_touch
remove_attribute find(cell, "vctacup1slmxac") dont_touch
remove_attribute find(cell, "vctclpsgnmuwb") dont_touch
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
report -reference > report/vuctlsl3.ref
report_area > report/vuctlsl3.area
report_net > report/vuctlsl3.net
report_constraint -all_violators > report/vuctlsl3.violators
report_timing -path full -delay max -max_paths 10 > report/vuctlsl3.full.paths
report_clock > report/vuctlsl3.clock
write -f edif -o vuctlsl3.edf -hier vuctlsl
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
report -reference > report/vuctlsl4.ref
report_area > report/vuctlsl4.area
report_net > report/vuctlsl4.net
report_constraint -all_violators > report/vuctlsl4.violators
report_timing -path full -delay max -max_paths 10 > report/vuctlsl4.full.paths
report_clock > report/vuctlsl4.clock
write -f edif -o vuctlsl4.edf -hier vuctlsl
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
report -reference > report/vuctlsl.ref
report_area > report/vuctlsl.area
report_net > report/vuctlsl.net
report_constraint -all_violators > report/vuctlsl.violators
report_timing -path full -delay max -max_paths 10 > report/vuctlsl.full.paths
report_clock > report/vuctlsl.clock
write -f edif -o vuctlsl.edf -hier vuctlsl
check_design > vuctlsl.lint
quit