/* setup aliases */

alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
				        set_wire_load 128000 -mode top;"

alias set_default_timing_constraints   "create_clock clk -period 15.5 -waveform {0 7.75}; \
					set_input_delay 15.0 -clock clk all_inputs(); \
					set_input_delay 8.25 clk; \
					set_output_delay 14.5 -clock clk all_outputs(); \
					set_driving_cell -none  {clk}; \
					set_driving_cell -cell in01d0  all_inputs(); \
					set_drive 0 {clk}; \
					set_load 1.0 all_outputs();"


/* setup the search path for includes */
search_path = search_path + "../src"

/* read the verilog sources */

read -f verilog ../src/vusl.v
read -f edif vuctl.edf
read -f edif vmult.edf
read -f edif vudp.edf

current_design = vusl

set_default_operating_conditions
set_default_timing_constraints

set_disable_timing su_cont_to_from
/*
set_disable_timing vuctl1/vctcontbus0nt
set_disable_timing vuctl1/vctcontbus1nt
set_disable_timing vuctl1/vctcontbus2nt
set_disable_timing vuctl1/vctcontbus3nt
*/

set_max_transition 2.0 current_design;

include vusl.con

link 

current_design = vusl

check_design > vusl.lint

compile_no_new_cells_at_top_level = "true"

current_design = vusl

write -f edif -o vusl.edf -hier vusl

report -reference > report/vusl.ref

report_area > report/vusl.area

report_net > report/vusl.net

report_constraint -all_violators > report/vusl.violators

report_timing -path full -delay max -max_paths 10 > report/vusl.full.paths

quit