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#!smake -J 1
#
#  This makefile has rules for making both the executables
#  which make up the simulator, and for running test cases.
#
# $Revision: 1.1.1.1 $
#
COMMONPREF=rcp
PRDEPTH = ../../..

include $(PRDEPTH)/PRdefs

#
# Directory to store verilog output files (simv, simv.daidir, csrc)
# All *.o and *.c files will be placed in $(SIMVDIR)/csrc
# User can overide this variable on make command line (i.e. make SIMVDIR=/tmp)
# or environment variable.
#
SIMVDIR		?= /var/tmp/$(USER)

#
# Tools
#
SIMV		= LD_LIBRARY_PATH=$(VCSDIR)/lib $(SIMVDIR)/simv -q

#
#  Directories
#
#
#  C Sources
#
#  Header file Directories
#
LCINCS 		= 
GCINCS 		=

#
# Compiler options
#
OPTIMIZER	= -g
LCOPTS		= -fullwarn

#
#  Verilog compiler options
#

# override GVCSOPTS
#
GVCSOPTS = -l vcs.log -M -Mupdate -Mmakep=pmake			\
	-CC "-Wab,-big_got -Wab,-dwalign" -lc -V 			\


LVCSOPTS = -y .								\
	-y $(PRDEPTH)/hw/chip/lib/verilog/pads				\
	-y $(PRDEPTH)/hw/chip/rcp/src					\
	-y $(PRDEPTH)/hw/chip/rcp/rdp/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ri/src				\
	-y $(PRDEPTH)/hw/chip/rcp/rsp/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ar/src				\
	-y $(PRDEPTH)/hw/chip/rcp/mi/src				\
	-y $(PRDEPTH)/hw/chip/rcp/vi/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ai/src				\
	-y $(PRDEPTH)/hw/chip/rcp/pi/src				\
	-y $(PRDEPTH)/hw/chip/rcp/si/src				\
	-y $(PRDEPTH)/hw/chip/rcp/cs/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ew/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ep/src				\
	-y $(PRDEPTH)/hw/chip/rcp/cv/src				\
	-y $(PRDEPTH)/hw/chip/rcp/st/src				\
	-y $(PRDEPTH)/hw/chip/rcp/tc/src				\
	-y $(PRDEPTH)/hw/chip/rcp/tm/src				\
	-y $(PRDEPTH)/hw/chip/rcp/tf/src				\
	-y $(PRDEPTH)/hw/chip/rcp/cc/src				\
	-y $(PRDEPTH)/hw/chip/rcp/bl/src				\
	-y $(PRDEPTH)/hw/chip/rcp/at/src				\
	-y $(PRDEPTH)/hw/chip/rcp/bl/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ms/src				\
	-y $(PRDEPTH)/hw/chip/rcp/rsp/src				\
	-y $(PRDEPTH)/hw/chip/rcp/su/src				\
	-y $(PRDEPTH)/hw/chip/rcp/vu/src				\
	-y $(PRDEPTH)/hw/chip/rcp/ls/src				\
	-y $(PRDEPTH)/hw/chip/rcp/is/src				\
	-y $(PRDEPTH)/hw/chip/rcp/io/src				\
	-y $(PRDEPTH)/hw/chip/rcp/dm/src				\
	-y $(PRDEPTH)/hw/chip/rcp/sb/src				\
	-y $(PRDEPTH)/hw/chip/rcp/su/fixes				\
	-y $(PRDEPTH)/hw/chip/rcp/div/src				\
	-y $(PRDEPTH)/hw/chip/rcp/tst/src				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/dp				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell			\
	-y $(PRDEPTH)/hw/chip/lib/verilog/ram				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/user				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rac/gate			\
	-y $(PRDEPTH)/hw/chip/lib/verilog/udp				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rdram/behavioral		\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rom/behavioral		\
	-y $(PRDEPTH)/hw/chip/lib/verilog/pif				\
	+libext+.v+.vzd+.vmd						\
	+incdir+$(PRDEPTH)/hw/chip/rcp/inc				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/su/src				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/vu/src				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/ms/src				\
	-Mdir=$(SIMVDIR)/csrc                                           \


GATE_LVCSOPTS = -y .							\
	-y $(PRDEPTH)/hw/chip/lib/verilog/pads				\
	-y $(PRDEPTH)/hw/chip/rcp/su/fixes				\
	-y $(PRDEPTH)/hw/chip/rcp/div/src				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/dp				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell			\
	-y $(PRDEPTH)/hw/chip/lib/verilog/ram				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/user				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rac/gate			\
	-y $(PRDEPTH)/hw/chip/lib/verilog/udp				\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rdram/behavioral		\
	-y $(PRDEPTH)/hw/chip/lib/verilog/rom/behavioral		\
	-y $(PRDEPTH)/hw/chip/lib/verilog/pif				\
	+libext+.v+.vzd+.vmd+.vsyn					\
	+incdir+$(PRDEPTH)/hw/chip/rcp/inc				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/su/src				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/vu/src				\
	+incdir+$(PRDEPTH)/hw/chip/rcp/ms/src				\
	-Mdir=$(SIMVDIR)/csrc                                           \

GATE_RCP = ./rcp.vsyn

# vudp and sudp must be removed from rcp.vsyn
GATE_FILES =								\
	$(GATE_RCP)							\
	$(PRDEPTH)/hw/chip/rcp/su/src/dprgf011h.v			\
	$(PRDEPTH)/hw/chip/rcp/su/src/sudp.v				\
	$(PRDEPTH)/hw/chip/rcp/vu/src/vudp.v				\
	$(PRDEPTH)/hw/chip/rcp/vu/src/dprgf020h.v			\
	$(PRDEPTH)/hw/chip/rcp/vu/src/div_rom.v


#
#  Compiling options for IPC version
#
GIPCOPTS =								\
	-q								\
	+acc								\
	+librescan							\
	+define+MMAP_RDRAM						\
	+define+IPC_PRESENT						\
	-P $(ROOT)/usr/lib/PR/rcppli.tab                                \
	$(ROOT)/usr/lib/PR/librcppli.a

IPCOPTS =	$(GIPCOPTS) +define+RSP_MON +define+RSP_PRESENT +define+MSPAN_MON
GATE_IPCOPTS =	$(GIPCOPTS) +define+GATE_LEVEL +define+RSP_PRESENT

#
#  Default Targets
#
TARGETS   = simv 

default install: $(TARGETS)


$(COMMONTARGS): $(COMMONPREF)$$@
	$(SUBDIRS_MAKERULE)

#
#  SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules


#
# Compile Verilog processes
#

simv: reality.v  $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(VCSOPTS) -P $(ROOT)/usr/lib/PR/rcppli.tab \
	$(ROOT)/usr/lib/PR/librcppli.a -o $(SIMVDIR)/$@ reality.v

simv_rdp: reality.v dummy_rsp.v $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(VCSOPTS) -o $(SIMVDIR)/$@ reality.v dummy_rsp.v 

simv_rsp: reality.v dummy_rdp.v $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(VCSOPTS) -o $(SIMVDIR)/$@ reality.v dummy_rdp.v 

simv_io: reality.v dummy_rsp.v dummy_rdp.v $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(VCSOPTS) -o $(SIMVDIR)/$@ reality.v dummy_rsp.v dummy_rdp.v 

ipc: reality.v  $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(VCSOPTS) $(IPCOPTS) -o $(SIMVDIR)/simv.ipc reality.v

ipc_gates: reality.v  $(_FORCE)
	VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
	$(VCS)  $(GATE_LVCSOPTS) $(GVCSOPTS) $(VVCSOPTS) $(GATE_IPCOPTS) \
	-o $(SIMVDIR)/simv.ipc.gates reality.v $(GATE_FILES)

gipc: reality.v  $(_FORCE)
        VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
        $(VCS)  $(VCSOPTS) $(GIPCOPTS) -o $(SIMVDIR)/simv.gipc reality.v dummy_rsp.v dummy_rdp.v

iorand.rdram:	iorand.data

#
# Tests
#
pif_test: $(_FORCE)
	$(SIMV) +test_4200_pif_wr4B +load_pif
	$(SIMV) +test_4200_pif_rd4Bcpu +load_pif
	$(SIMV) +test_4200_pif_wr_rd +load_pif
	$(SIMV) +test_4200_pif_rd_lap1 +load_pif
	$(SIMV) +test_4200_pif_rd_lap2 +load_pif
	$(SIMV) +test_4200_pif_rd_lap3 +load_pif
	$(SIMV) +test_4200_pif_io_read_conflict +load_pif

nmi_test:  $(_FORCE)
	$(SIMV) +test_4200_nmi_test +enable_nmi

audio_test: $(_FORCE)
	$(SIMV) +test_4200_ai_test

video_test: $(_FORCE)
	$(SIMV) +test_4200_vi_test

bigtest: $(_FORCE)
	$(ROOT)/PR/iosim/src/iorand -d 0x241 -l io.log -i 10000 -r 10000 -t 4,7,12,8,15 -s "$(SIMVDIR)/simv.ipc -l verilog.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=rdram_0 +vitab=vi.tab +cbus_mon +rsp_mon +show_imem_on_r1 +vi_dump -vcd /var/tmp/kluster/bigtest.dump"
	
bigtest.rgb: vi.tab
	- rm Nlan1.rgb Nlan2.rgb Nlpn1.rgb Nhan1.rgb Nhpf2.rgb
	$(ROOT)/usr/sbin/vparse -i vi.tab -o big5.tab -f 2
	$(ROOT)/usr/sbin/monitor -i big5.tab000 -o Nlan1.rgb -h 0x00200044 -v 0x0050025
	$(ROOT)/usr/sbin/monitor -i big5.tab001 -o Nlan2.rgb -h 0x00200044 -v 0x0050025
	$(ROOT)/usr/sbin/monitor -i big5.tab002 -o Nlpn1.rgb -h 0x00200040 -v 0x0050025
	$(ROOT)/usr/sbin/monitor -i big5.tab003 -o Nhan1.rgb -h 0x00200044 -v 0x0050025
	$(ROOT)/usr/sbin/monitor -i big5.tab004 -o Nhpf2.rgb -h 0x00200044 -v 0x0050025
	$(ROOT)/usr/sbin/idiff Nlan1.rgb $(ROOT)/PR/rdpsim/backend/test/Iosim/lan1.rgb
	$(ROOT)/usr/sbin/idiff Nlan2.rgb $(ROOT)/PR/rdpsim/backend/test/Iosim/lan2.rgb
	$(ROOT)/usr/sbin/idiff Nlpn1.rgb $(ROOT)/PR/rdpsim/backend/test/Iosim/lpn1.rgb
	$(ROOT)/usr/sbin/idiff Nhan1.rgb $(ROOT)/PR/rdpsim/backend/test/Iosim/han1.rgb
	$(ROOT)/usr/sbin/idiff Nhpf2.rgb $(ROOT)/PR/rdpsim/backend/test/Iosim/hpf2.rgb

mlf2test: $(_FORCE)
	$(ROOT)/PR/iosim/src/iorand -d 0x241 -l io-mlf2.log -i 10000 -r 10000 -t 4,7,12,8,17 -s "$(SIMVDIR)/simv.ipc -l verilog-mlf2.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=rdram_0 +vitab=vi-mlf2.tab +cbus_mon +rsp_mon +show_imem_on_r1 +vi_dump -vcd /var/tmp/kluster/mlf2test.dump"

mlf2test.rgb: vi-mlf2.tab
	- rm Nmlf2.rgb* mlf2.tab*
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mlf2.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmlf2.rgb -h 0x00200044 -v 0x0050025

mlf2temp: $(_FORCE)
	$(ROOT)/PR/iosim/src/iorand -d 0x241 -l io-mlf2.log -i 10000 -r 10000 -t 4,7,8,18,17 -s "$(SIMVDIR)/simv.ipc -l verilog-mlf2.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=rdram_0 +vitab=vi-mlf2.tab +cbus_mon -vcd /var/tmp/kluster/mlf2temp.dump"


simenv : $(_FORCE)
	echo " setenv LD_LIBRARY_PATH $(VCSDIR)/lib "  > Setenv
	echo "enter command%  source Setenv"

# New 5 tests

mln1test: $(_FORCE)
	/usr/bsd/uncompress -c virdram.rdram.Z > virdram.rdram
	$(ROOT)/PR/iosim/src/iorand -o `date +%d%H%M%S` -C -R -d 0x241 -l io-mln1.log -i 10000 -r 10000 -t 4,7,15,8,16 -s "$(SIMVDIR)/simv.ipc -l verilog-mln1.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=virdram +vitab=vi-mln1.tab +cbus_mon +rsp_mon +show_imem_on_r1 -vcd /var/tmp/kluster/mln1test.dump"

mln1test.rgb: vi-mln1.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmln1.rgb
	- rm vi-mln1.rgb* vi-mln1.tab???
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mln1.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmln1.rgb -h 0x00200044 -v 0x0050025

mln2test: $(_FORCE)
	/usr/bsd/uncompress -c virdram.rdram.Z > virdram.rdram
	$(ROOT)/PR/iosim/src/iorand -o `date +%d%H%M%S` -C -R -d 0x241 -l io-mln2.log -i 10000 -r 10000 -t 4,7,15,8,17 -s "$(SIMVDIR)/simv.ipc -l verilog-mln2.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=virdram +vitab=vi-mln2.tab +cbus_mon +rsp_mon +show_imem_on_r1 -vcd /var/tmp/kluster/mln2test.dump"

mln2test.rgb: vi-mln2.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmln2.rgb
	- rm vi-mln2.rgb* vi-mln2.tab???
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mln2.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmln2.rgb -h 0x00200044 -v 0x0050025

mlp1test: $(_FORCE)
	/usr/bsd/uncompress -c virdram.rdram.Z > virdram.rdram
	$(ROOT)/PR/iosim/src/iorand -o `date +%d%H%M%S` -C -R -d 0x241 -l io-mlp1.log -i 10000 -r 10000 -t 4,7,15,8,18 -s "$(SIMVDIR)/simv.ipc -l verilog-mlp1.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=virdram +vitab=vi-mlp1.tab +cbus_mon +rsp_mon +show_imem_on_r1  -vcd /var/tmp/kluster/mlp1test.dump"

mlp1test.rgb: vi-mlp1.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmlp1.rgb
	- rm vi-mlp1.rgb* vi-mlp1.tab???
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mlp1.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmlp1.rgb -h 0x00200040 -v 0x0050025

mhn1test: $(_FORCE)
	/usr/bsd/uncompress -c virdram.rdram.Z > virdram.rdram
	$(ROOT)/PR/iosim/src/iorand -o `date +%d%H%M%S` -C -R -d 0x241 -l io-mhn1.log -i 10000 -r 10000 -t 4,7,15,8,19 -s "$(SIMVDIR)/simv.ipc -l verilog-mhn1.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=virdram +vitab=vi-mhn1.tab +cbus_mon +rsp_mon +show_imem_on_r1  -vcd /var/tmp/kluster/mhn1test.dump"

mhn1test.rgb: vi-mhn1.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmhn1.rgb
	- rm vi-mhn1.rgb* vi-mhn1.tab???
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mhn1.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmhn1.rgb -h 0x00200044 -v 0x0050025

mhf2test: $(_FORCE)
	/usr/bsd/uncompress -c virdram.rdram.Z > virdram.rdram
	$(ROOT)/PR/iosim/src/iorand -o `date +%d%H%M%S` -C -R -d 0x241 -l io-mhf2.log -i 10000 -r 10000 -t 4,7,15,8,20 -s "$(SIMVDIR)/simv.ipc -l verilog-mhf2.log +load_imem +load_dmem +load_pif +load_rom +mmap_rdram=virdram +vitab=vi-mhf2.tab +cbus_mon +rsp_mon +show_imem_on_r1  +vi_dump -vcd /var/tmp/kluster/mhf2test.dump"

mhf2test.rgb: vi-mhf2.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmhf2.rgb
	- rm vi-mhf2.rgb* vi-mhf2.tab???
	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-mhf2.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Nmhf2.rgb -h 0x00200044 -v 0x0050025

dth2test: $(_FORCE)
	- /usr/bsd/uncompress -c dither.rdram.Z > dither.rdram
	$(ROOT)/PR/iosim/src/iorand -C -d 0x241 -l io-dth2.log -i 10000 -r 10000 -t 21 -s "$(SIMVDIR)/simv.ipc -l verilog-dth2.log +mmap_rdram=dither +vitab=vi-dth2.tab +cbus_mon"

dth2test.rgb: vi-dth2.tab $(ROOT)/PR/rdpsim/backend/test/Iosim/Ndth2.rgb
	- rm vi-dth2.rgb* vi-dth2.tab???
 	$(ROOT)/PR/rdpsim/backend/diffvideo -i vi-dth2.tab -g $(ROOT)/PR/rdpsim/backend/test/Iosim/Ndth2.rgb -h 0x00200040 -v 0x0050045