cg.v
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// $Id: cg.v,v 1.1.1.1 2002/05/17 06:07:50 blythe Exp $
`timescale 1ns/100ps
module cg(clock, reset_l, bus_clk, vbus_clock);
`include "reality.vh"
`include "define.vh"
parameter RAMBUS_CLOCK_PERIOD = 4.0; // 250 MHz Rambus
input reset_l;
input clock;
output bus_clk;
output vbus_clock;
reg bus_clk;
reg vbus_clock;
integer clock_count;
initial bus_clk = HIGH;
// freeze vclk flag
reg freeze_vclk;
initial freeze_vclk = LOW;
initial
begin
if ($test$plusargs("rcp_test_tssi"))
vbus_clock = LOW;
else
vbus_clock = HIGH;
end
always #(RAMBUS_CLOCK_PERIOD / 2) bus_clk = ~bus_clk;
always #(RAMBUS_CLOCK_PERIOD * 2)
begin
if ($test$plusargs("rcp_test_tssi"))
vbus_clock = ~vbus_clock || freeze_vclk;
end
always #((RAMBUS_CLOCK_PERIOD * 5 )/ 2)
begin
if (!$test$plusargs("rcp_test_tssi"))
vbus_clock = ~vbus_clock;
end
always @(posedge clock) clock_count <= reset_l ? clock_count + 1 : 0;
endmodule