dr_state.tdf
10.5 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
TITLE "$Id: dr_state.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc. ";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, 1995 Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
INCLUDE "rcpproto.inc";
subdesign dr_state
(
clock, rstB, rst_d, gio_ras_state, gio_start, gio_rd, gio_halfcnt, refresh_inc,
block_access, cart_enable, cart_wr, cart_rd, cart_rd_d, cart_banksel
: input;
rasB, casB, weB, oeB, dr_cntl[2..0], gio_start_ack, gio_latch, gio_output
: output;
)
variable
gio_start_ack, gio_latch, gio_output : node;
dr_cntl[2..0], refresh_cnt[1..0], refresh_dec, refresh_start,
rasB, casB, weB, oeB : dff;
dramstate: MACHINE of bits (drstate[4..0]) with states (
idle = B"00000", % 11111 %
ras_assert_gio1 = B"01001", % 01111 %
ras_assert_gio2 = B"01000", % 01111 %
cas_adr_wr_gio = B"01111", % 01011 %
cas_assert_wr_gio1 = B"01110", % 00011 %
cas_assert_wr_gio2 = B"01101", % 00011 %
cas_adr_rd_gio = B"00111", % 01111 %
cas_assert_rd_gio1 = B"00110", % 00101 %
cas_assert_rd_gio2 = B"00101", % 00101 %
cas_assert_rd_gio3 = B"00100", % 00101 %
cas_assert_rd_gio4 = B"01100", % 00101 %
cas_assert_refresh = B"01011", % 10111 %
ras_assert_refresh1 = B"01010", % 00111 %
ras_assert_refresh2 = B"11011", % 00111 %
ras_assert_refresh3 = B"11010", % 00111 %
ras_assert_refresh4 = B"11001", % 00111 %
ras_assert_refresh5 = B"11000", % 00111 %
ras_adr_cart1 = B"10011", % 11111 %
ras_adr_cart2 = B"10010", % 11111 %
ras_assert_cart1 = B"10001", % 01110 %
ras_assert_cart2 = B"10000", % 01110 %
cas_wait_rd_cart = B"11100", % 01110 %
cas_delay_wr_cart = B"11111", % 01010 %
cas_assert_wr_cart1 = B"11110", % 00010 %
cas_assert_wr_cart2 = B"11101", % 00011 %
cas_wait_wr_cart = B"10100", % 01011 %
ras_delay1 = B"00011", % 11111 %
ras_delay2 = B"00010", % 11111 %
ras_delay3 = B"00001" % 11111 %
);
begin
refresh_dec.clk = clock;
refresh_dec = (dramstate == cas_assert_refresh);
refresh_start.clk = clock;
refresh_start = (refresh_inc # (refresh_cnt[] != 0)) & !block_access;
refresh_cnt[].clk = clock;
if (rst_d & rstB) then refresh_cnt[] = 2;
elsif (refresh_inc & !refresh_dec) then
refresh_cnt[] = (refresh_cnt[1] # refresh_cnt[0], !refresh_cnt[1]);
elsif (!refresh_inc & refresh_dec) then
refresh_cnt[] = (refresh_cnt[1] & !refresh_cnt[0], refresh_cnt[1]);
else
refresh_cnt[] = refresh_cnt[];
end if;
gio_start_ack = (dramstate == ras_assert_gio1);
gio_latch = (dramstate == cas_assert_rd_gio2)
# (dramstate == cas_assert_rd_gio3);
gio_output = (dramstate == cas_adr_wr_gio) # (dramstate == cas_assert_wr_gio1);
dr_cntl[].clk = clock;
dr_cntl[].clrn = rstB;
if (!refresh_start & cart_enable & !block_access
& ((dramstate == idle) # (dramstate == ras_delay3))) then
dr_cntl[] = CART_RAS;
elsif (cart_enable & (dramstate == ras_assert_cart1)) then
dr_cntl[] = CART_CAS1;
elsif (cart_enable
& ((dramstate == cas_assert_wr_cart1)
# (((dramstate == ras_assert_cart2) # (dramstate == cas_wait_rd_cart))
& cart_banksel & cart_rd & !cart_rd_d))) then
dr_cntl[] = CART_CAS2;
elsif (!cart_enable & gio_ras_state) then dr_cntl[] = GIO_RAS;
elsif (!cart_enable & (dramstate == ras_assert_gio1)) then
dr_cntl[] = GIO_CAS1;
elsif (((dramstate == cas_assert_rd_gio1) # (dramstate == cas_assert_wr_gio1))
& gio_halfcnt & !cart_enable) then
dr_cntl[] = GIO_CAS2;
else
dr_cntl[] = DR_IDLE;
end if;
rasB.clk = clock;
case dramstate is
% gio bus transactions %
WHEN idle =>
if (!refresh_start & !cart_enable & gio_start) then rasB = gnd;
else rasB = vcc;
end if;
WHEN cas_assert_wr_gio2, cas_assert_rd_gio4 =>
if (gio_halfcnt) then rasB = gnd;
else rasB = vcc;
end if;
WHEN ras_assert_cart2 => % waiting for ad16 wr/rd pulses %
if (!cart_enable) then rasB = vcc;
else rasB = gnd;
end if;
WHEN cas_wait_rd_cart =>
if (!cart_rd & !cart_banksel) then rasB = vcc;
else rasB = gnd;
end if;
WHEN cas_wait_wr_cart =>
if (!cart_banksel # !cart_enable) then rasB = vcc;
else rasB = gnd;
end if;
WHEN ras_assert_gio1, ras_assert_gio2, cas_adr_wr_gio, cas_assert_wr_gio1,
cas_adr_rd_gio, cas_assert_rd_gio1, cas_assert_rd_gio2,
cas_assert_rd_gio3, cas_assert_refresh, ras_assert_refresh1,
ras_assert_refresh2, ras_assert_refresh3, ras_assert_refresh4,
ras_adr_cart2, ras_assert_cart1, ras_assert_cart2, cas_delay_wr_cart,
cas_assert_wr_cart1, cas_assert_wr_cart2 => rasB = gnd;
WHEN others => rasB = vcc;
end case;
casB.clk = clock;
case dramstate is
WHEN ras_delay3, idle =>
if (refresh_start) then casB = gnd;
else casB = vcc;
end if;
WHEN cas_adr_wr_gio, cas_assert_wr_gio1, cas_adr_rd_gio,
cas_assert_rd_gio1, cas_assert_rd_gio2, cas_assert_rd_gio3,
cas_assert_refresh, ras_assert_refresh1, ras_assert_refresh2,
ras_assert_refresh3, ras_assert_refresh4, cas_delay_wr_cart,
cas_assert_wr_cart1 => casB = gnd;
WHEN others => casB = vcc;
end case;
weB.clk = clock;
weB.prn = rstB;
case dramstate is
WHEN ras_assert_gio2 =>
if (gio_rd) then weB = vcc;
else weB = gnd;
end if;
WHEN cas_adr_wr_gio, cas_assert_wr_gio1,
cas_assert_wr_gio2 => weB = gnd;
WHEN ras_assert_cart2, cas_wait_wr_cart => % waiting for ad16 wr pulses %
if (cart_wr & cart_banksel) then weB = gnd;
else weB = vcc;
end if;
WHEN cas_delay_wr_cart, cas_assert_wr_cart1,
cas_assert_wr_cart2 => weB = gnd;
WHEN others => weB = vcc;
end case;
oeB.clk = clock;
case dramstate is
WHEN cas_adr_rd_gio, cas_assert_rd_gio1,
cas_assert_rd_gio2, cas_assert_rd_gio3 => oeB = gnd;
WHEN others => oeB = vcc;
end case;
dramstate.clk = clock;
dramstate.reset = !rstB;
case dramstate is
% gio bus transactions %
WHEN ras_assert_gio1 => dramstate = ras_assert_gio2;
WHEN ras_assert_gio2 =>
if (gio_rd) then dramstate = cas_adr_rd_gio;
else dramstate = cas_adr_wr_gio;
end if;
WHEN cas_adr_wr_gio => dramstate = cas_assert_wr_gio1;
WHEN cas_assert_wr_gio1 => dramstate = cas_assert_wr_gio2;
WHEN cas_assert_wr_gio2 =>
if (gio_halfcnt) then dramstate = cas_adr_wr_gio;
else dramstate = ras_delay1;
end if;
WHEN cas_adr_rd_gio => dramstate = cas_assert_rd_gio1;
WHEN cas_assert_rd_gio1 => dramstate = cas_assert_rd_gio2;
WHEN cas_assert_rd_gio2 => dramstate = cas_assert_rd_gio3;
WHEN cas_assert_rd_gio3 => dramstate = cas_assert_rd_gio4;
WHEN cas_assert_rd_gio4 =>
if (gio_halfcnt) then dramstate = cas_adr_rd_gio;
else dramstate = ras_delay1;
end if;
% cas before ras refresh cycle %
WHEN cas_assert_refresh => dramstate = ras_assert_refresh1;
WHEN ras_assert_refresh1 => dramstate = ras_assert_refresh2;
WHEN ras_assert_refresh2 => dramstate = ras_assert_refresh3;
WHEN ras_assert_refresh3 => dramstate = ras_assert_refresh4;
WHEN ras_assert_refresh4 => dramstate = ras_assert_refresh5;
WHEN ras_assert_refresh5 => dramstate = ras_delay1;
% cartridge (ad16) bus transactions %
% ras address is latched at the end of ras_adr_cart1 cycle %
WHEN ras_adr_cart1 => dramstate = ras_adr_cart2;
WHEN ras_adr_cart2 => dramstate = ras_assert_cart1;
WHEN ras_assert_cart1 => dramstate = ras_assert_cart2;
WHEN ras_assert_cart2 => % waiting for ad16 wr/rd pulses %
if (!cart_enable) then dramstate = ras_delay1;
elsif (cart_rd & !cart_rd_d & cart_banksel) then
dramstate = cas_wait_rd_cart;
elsif (cart_wr & cart_banksel) then dramstate = cas_delay_wr_cart;
else dramstate = ras_assert_cart2;
end if;
WHEN cas_wait_rd_cart =>
if (!cart_rd & !cart_banksel) then dramstate = ras_delay1;
else dramstate = cas_wait_rd_cart;
end if;
WHEN cas_delay_wr_cart => % 1 cycle delay for write setup %
dramstate = cas_assert_wr_cart1;
WHEN cas_assert_wr_cart1 => dramstate = cas_assert_wr_cart2;
WHEN cas_assert_wr_cart2 => dramstate = cas_wait_wr_cart;
WHEN cas_wait_wr_cart =>
if (!cart_banksel # !cart_enable) then dramstate = ras_delay1;
elsif (cart_wr) then dramstate = cas_delay_wr_cart;
else dramstate = cas_wait_wr_cart;
end if;
% delay for ras precharge (at the end of every cycle %
WHEN ras_delay1 => dramstate = ras_delay2;
WHEN ras_delay2 => dramstate = ras_delay3;
WHEN ras_delay3 =>
if (refresh_start) then dramstate = cas_assert_refresh;
elsif (cart_enable & !block_access) then dramstate = ras_adr_cart1;
else dramstate = idle;
end if;
WHEN others =>
if (refresh_start) then dramstate = cas_assert_refresh;
elsif (cart_enable & !block_access) then dramstate = ras_adr_cart1;
elsif (gio_start) then dramstate = ras_assert_gio1;
else dramstate = idle;
end if;
end case;
end;