fakepif.tdf
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TITLE "$Header: /root/leakn64/depot/rf/sw/n64os20l/hw/proto/pgm/fakepif.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
constant IDLE = 0;
constant PIDLE = 4; % alternate idle (not used) %
constant ADDRESS = 1; % loading address from serial port %
constant PADDR = 5; % alternate address (not used) %
constant WAIT = 2; % waiting for start for write data %
constant PWAIT = 6; % alternate wait (not used) %
constant WRITE = 3; % loading write data from serial port %
constant READ = 7; % copying read data from rom to serial port %
subdesign fakepif
(
%pif interface%
PChClk, PChCmd, CldRstB : INPUT;
PChRsp : OUTPUT;
%rom interface%
datain[7..0] : INPUT;
csB, adr[10..0] : OUTPUT;
)
variable
clock : NODE;
adr[10..0], data[7..0], bitcnt[3..0], bytecnt[5..0],
state[2..0] : DFF;
begin
clock = global(PChClk);
PChRsp = data[7];
csB = !state[2];
state[].clk = clock;
state[].clrn = CldRstB;
if (((state[] == IDLE) # (state[] == PIDLE)) & !PChCmd) then
%start bit for address%
state[] = ADDRESS;
elsif (((state[] == ADDRESS) # (state[] == PADDR)) & (bitcnt[] == 0) & adr[10])
then
state[] = READ;
elsif (((state[] == ADDRESS) # (state[] == PADDR)) & (bitcnt[] == 0)
& !adr[10]) then
state[] = WAIT;
elsif (((state[] == WAIT) # (state[] == PWAIT)) & !PChCmd) then
state[] = WRITE;
elsif (((state[] == WRITE) # (state[] == READ))
& (bytecnt[] == 0) & (bitcnt[] == 0)) then
state[] = IDLE;
else
state[] = state[];
end if;
data[].clk = clock;
data[].prn = CldRstB;
if ((state[] == READ) & (bitcnt[] == 0)) then
data[] = datain[]; %data from rom%
elsif (((state[] == ADDRESS) # (state[] == PADDR)) & (bitcnt[] == 0)) then
data[] = (data[6..0], 0); %start bit for read data, ack for write data%
else
data[] = (data[6..0], 1); %shift left and fill with 1%
end if;
adr[].clk = clock;
if ((state[] == ADDRESS) # (state[] == PADDR)) then
%loading address from serial port%
adr[] = (adr[9..2], PChCmd, B"00");
elsif (((state[] == READ) # (state[] == WRITE)) & (bitcnt[] == 0)) then
adr[10..6] = adr[10..6];
adr[5..0] = adr[5..0] + 1;
else
adr[] = adr[];
end if;
bytecnt[].clk = clock;
bytecnt[].clrn = CldRstB;
if (((state[] == ADDRESS) # (state[] == PADDR)) & (bitcnt[] == 1)) then
bytecnt[] = (!adr[10],!adr[10],!adr[10],!adr[10],1,1);
elsif (((state[] == WRITE) # (state[] == READ)) & (bitcnt[] == 0)) then
bytecnt[] = bytecnt[] - 1;
else
bytecnt[] = bytecnt[];
end if;
bitcnt[].clk = clock;
bitcnt[].clrn = CldRstB;
if (((state[] == IDLE) # (state[] == PIDLE)) & !PChCmd) then %start bit for address%
bitcnt[] = 10;
elsif (((state[] == ADDRESS) # (state[] == PADDR)) & (bitcnt[] == 0)) then
bitcnt[] = 7; % load and shift 1st word for read %
elsif (((state[] == WAIT) # (state[] == PWAIT)) & !PChCmd) then
bitcnt[] = 7; % start of 1st word for write %
elsif (((state[] == READ) # (state[] == WRITE)) & (bitcnt[] == 0)) then
bitcnt[] = 7;
elsif (bitcnt[] != 0) then
bitcnt[] = bitcnt[] - 1;
else
bitcnt[] = bitcnt[];
end if;
end;