dpadd001s.vmd
2.41 KB
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/* %W% updated by Chunling liu on %T% %G% */
/**************************************************************/
/* Verilog module of datapath cell dpadd001s */
/* Designed by Chunling Liu Compass July 27, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* B : the input port */
/* SO : the output port */
/* Control ports */
/* INST_CIN : the carry input */
/* INST_COUT : the carry output */
/* INST_OVR : the overflow output */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpadd001s(A, B, SO, INST_CIN, INST_COUT, INST_OVR);
parameter WORDSIZE = 8, DELAY = 15, BF = 1;
input [WORDSIZE-1:0] A, B;
output [WORDSIZE-1:0] SO;
input INST_CIN;
output INST_COUT, INST_OVR;
reg [WORDSIZE:0] carry;
function [WORDSIZE-1:0] add;
input [WORDSIZE-1:0] a,b;
input cin ;
integer i;
begin
carry[0] = cin;
for (i=0; i<WORDSIZE; i=i+1)
begin
add[i] = a[i] ^ b[i] ^ carry[i];
carry[i+1] = (a[i]&b[i]) |
(a[i]&carry[i]) |
(b[i]&carry[i]) ;
end
if (BF != 1)
case(WORDSIZE)
3,4,5,8,10,11,12,14,17,19,21,22,23,25,27,30,32,34,36,
37,38,40,42,47,49,51,53,55,56,57,59,61,63,65,68,70,72,
74,76,78,80: carry[WORDSIZE] = ~ carry[WORDSIZE];
default: ;
endcase
// case(WORDSIZE-1)
// 3,4,5,8,10,11,12,14,17,19,21,22,23,25,27,30,32,34,36,
// 37,38,40,42,47,49,51,53,55,56,57,59,61,63,65,68,70,72,
// 74,76,78,80: carry[WORDSIZE-1] = ~ carry[WORDSIZE-1];
// default: ;
// endcase
end
endfunction
assign #DELAY
SO = add(A,B,INST_CIN),
INST_COUT = carry[WORDSIZE],
INST_OVR = carry[WORDSIZE-1];
endmodule