dpadd002h.vmd
2.16 KB
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/**************************************************************/
/* Verilog module of datapath cell DPADD002H */
/* Designed by Lin Yang VLSI Technology Feb. 01, 91 */
/* Designed by Chunling Liu Compass June 08,1992 */
/* Designed by Linda J. Xu Compass Feb. 04,1993 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* B : the input port */
/* CIN : the carry input */
/* SO : the output port */
/* COUT : the carry output */
/* Control ports */
/* INST_OVR : the carry overflow flag output */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpadd002h(A, B, CIN, SO, COUT, INST_OVR);
parameter WORDSIZE = 8, DELAY = 15, BF = 1;
input [WORDSIZE-1:0] A, B, CIN;
output [WORDSIZE-1:0] SO, COUT;
output INST_OVR;
reg [WORDSIZE:0] carry;
reg odd;
function [WORDSIZE-1:0] add;
input [WORDSIZE-1:0] a, b, cin;
integer i;
begin
odd = WORDSIZE % 2;
carry[0] = cin[0];
for (i=0; i<WORDSIZE; i=i+1)
begin
add[i] = a[i] ^ b[i] ^ carry[i];
carry[i+1] = (a[i]&b[i]) |
(a[i]&carry[i]) |
(b[i]&carry[i]) ;
end
end
endfunction
assign #DELAY
COUT[WORDSIZE-2:0] = {WORDSIZE-1{1'b0}},
COUT[WORDSIZE-1] = carry[WORDSIZE],
INST_OVR = ((BF == 0) & odd) ?
~carry[WORDSIZE-1]: carry[WORDSIZE-1],
SO = add(A,B,CIN);
endmodule