dpalu001s.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpalu001s */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* B : the input port */
/* SO : the output port */
/* INST_OVR : the selected carrry output port */
/* Control ports */
/* INST_CIN : the carry input */
/* INST : the operation control input */
/* INST_COUT : the carry output */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpalu001s(A, B, SO, INST_CIN, INST, INST_COUT, INST_OVR );
parameter WORDSIZE = 8, DELAY = 15, BF = 1;
input [WORDSIZE-1:0] A, B;
output [WORDSIZE-1:0] SO;
input INST_CIN;
input [4:0] INST;
output INST_COUT, INST_OVR;
reg [WORDSIZE:0] carry;
function [WORDSIZE-1:0] alu;
input [WORDSIZE-1:0] a,b;
input cin;
input [4:0]op;
integer i;
reg [WORDSIZE-1 : 0] a1, b1, p, q;
begin
carry[WORDSIZE:1] = {WORDSIZE{1'b0}};
carry[0] = cin;
if (op[3:0] == 4'b1000) alu = a ^ b;
else if (op[3:0] == 4'b1001) alu = a ^ ~b;
else if (op[3:0] == 4'b1010) alu = a ^ ~b;
else if (op[3:0] == 4'b1011) alu = a ^ b;
else if (op[3:0] == 4'b1100) alu = ~(a & b);
else if (op[3:0] == 4'b1101) alu = a | ~b;
else if (op[3:0] == 4'b1110) alu = ~a | b;
else if (op[3:0] == 4'b1111) alu = a | b;
else if (op[4:0] == 5'b10000) alu = a ^ ~b;
else if (op[4:0] == 5'b10001) alu = a ^ b;
else if (op[4:0] == 5'b10010) alu = a ^ b;
else if (op[4:0] == 5'b10011) alu = a ^ ~b;
else if (op[4:0] == 5'b10100) alu = a & b;
else if (op[4:0] == 5'b10101) alu = ~a & b;
else if (op[4:0] == 5'b10110) alu = a & ~b;
else if (op[4:0] == 5'b10111) alu = ~(a | b);
else if (op[4:3] == 2'b00)
begin
for (i=0; i<WORDSIZE; i=i+1)
begin
a1 = a[i] ^op[0];
b1 = b[i] ^op[1];
p = a1 ^ (~b1);
q = a1 & b1;
carry[i+1] = ((~p) & carry[i]) | (p & q);
end
case (op[2:0])
3'b000 :
alu = a ^ b ^ carry[WORDSIZE-1 : 0];
3'b001 :
alu = a ^~ b ^ carry[WORDSIZE-1 : 0];
3'b010 :
alu = a ^~ b ^ carry;
3'b011 :
alu = a ^ b ^ carry;
3'b100 :
alu = (~(a & b)) ^ carry;
3'b101 :
alu = (a | (~b)) ^ carry;
3'b110 :
alu = ((~a) | b) ^ carry;
3'b111 :
alu = (a | b) ^ carry;
default
begin
alu = {WORDSIZE{1'bx}};
carry = {(WORDSIZE+1){1'bx}};
end
endcase
end
else
begin
alu = {WORDSIZE{1'bx}};
carry = {(WORDSIZE+1){1'bx}};
end
if (BF != 1)
case(WORDSIZE)
3,4,5,8,10,11,12,14,17,19,21,22,23,25,27,30,32,34,36,
37,38,40,42,47,49,51,53,55,56,57,59,61,63,65,68,70,72,
74,76,78,80: carry[WORDSIZE] = ~ carry[WORDSIZE];
default: ;
endcase
case(WORDSIZE-1)
3,4,5,8,10,11,12,14,17,19,21,22,23,25,27,30,32,34,36,
37,38,40,42,47,49,51,53,55,56,57,59,61,63,65,68,70,72,
74,76,78,80: carry[WORDSIZE-1] = ~ carry[WORDSIZE-1];
default: ;
endcase
end
endfunction
assign #DELAY
SO = alu(A,B,INST_CIN,INST),
INST_COUT = carry[WORDSIZE],
INST_OVR = carry[WORDSIZE-1];
endmodule