/**************************************************************/
/*    Verilog module of datapath cell DPAND0021               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by  Linda J. Xu                    July, 1992  */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A1   : the input port                               */
/*        A2   : the input port                               */
/*        Z    : the output port                              */
/*        ZN   : the output port                              */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpand0021(A1, A2, Z, ZN);

  parameter WORDSIZE = 8, DELAY = 3, BF = 1;
  input  [WORDSIZE-1:0] A1, A2;
  output [WORDSIZE-1:0] Z, ZN;
  wire [WORDSIZE-1:0] #DELAY Z = A1 & A2, ZN = ~(A1 & A2);

endmodule