/**************************************************************/
/*    Verilog module of datapath cell DPAOI0011               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu                 July, 1992   */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A1   : the input port                               */
/*        A2   : the input port                               */
/*        B1   : the input port                               */
/*        B2   : the input port                               */
/*        ZN   : the output port                              */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpaoi0011(A1, A2, B1, B2, ZN);

  parameter WORDSIZE = 8, DELAY = 2, BF = 1;
  input  [WORDSIZE-1:0] A1, A2, B1, B2;
  output [WORDSIZE-1:0] ZN;
  wire   [WORDSIZE-1:0] #DELAY ZN = ~((B1 & B2) | (A1 & A2));

endmodule