dpasb001h.vmd
2.24 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
/**************************************************************/
/* Verilog module of datapath cell dpasb001h */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Chunling Liu Compass June 10, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port (+) */
/* B : the input port (+/-) */
/* SO : the output port */
/* Control ports */
/* INST_CIN : the carry input */
/* INST : the operation control input */
/* INST_COUT : the carry output */
/* INST_OVR : the carry overflow flag output */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpasb001h(A, B, SO, INST_CIN, INST, INST_COUT, INST_OVR);
parameter WORDSIZE = 8, DELAY = 15, BF = 1;
input [WORDSIZE-1:0] A, B;
output [WORDSIZE-1:0] SO;
input INST_CIN, INST;
output INST_COUT, INST_OVR;
reg [WORDSIZE:0] carry;
function [WORDSIZE-1:0] asb;
input [WORDSIZE-1:0] a,b;
reg [WORDSIZE-1:0] b1;
input cin;
input op;
integer i;
begin
carry[0] = cin;
for (i=0; i<WORDSIZE; i=i+1)
begin
b1[i] = (INST == 1) ?
!b[i]: b[i];
asb[i] = a[i] ^ b1[i] ^ carry[i];
carry[i+1] = (a[i]&b1[i]) |
(a[i]&carry[i]) |
(b1[i]&carry[i]) ;
end
end
endfunction
assign #DELAY
SO = asb(A,B,INST_CIN,INST),
INST_COUT = carry[WORDSIZE],
INST_OVR = carry[WORDSIZE-1];
endmodule