dpasb002s.vmd
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/**************************************************************/
/* Verilog module of datapath cell DPASB002S */
/* Designed by Lin Yang VLSI Technology Oct. 30, 90 */
/* Designed by Linda J. Xu Compass Feb. 4, 93 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port (+/-) */
/* B : the input port (+/-) */
/* SO : the output port */
/* STATUS : the selected carrry output port */
/* Control ports */
/* INST_SA : the subtract A control input */
/* INST_SB : the subtract B control input */
/* INST_CIN : the carry input */
/* INST_COUT : the carry output */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpasb002s(A, B, SO, STATUS, INST_SA, INST_SB, INST_CIN, INST_COUT);
parameter WORDSIZE = 8, DELAY = 15, BF = 1;
input [WORDSIZE-1:0] A, B;
output [WORDSIZE-1:0] SO, STATUS;
input INST_SA, INST_SB, INST_CIN;
output INST_COUT;
reg [WORDSIZE:0] carry;
reg [WORDSIZE-1:0] stat;
function [WORDSIZE-1:0] asb;
input [WORDSIZE-1:0] a,b;
input cin;
input sa, sb;
reg [WORDSIZE-1:0] a1, b1;
integer i;
begin
carry[0] = cin;
case ({sa})
1'b0:
a1 = a;
1'b1:
for (i=0; i<WORDSIZE; i=i+1)
a1[i] = ~a[i];
default
a1 = {WORDSIZE{1'bx}};
endcase
case ({sb})
1'b0:
b1 = b;
1'b1:
for (i=0; i<WORDSIZE; i=i+1)
b1[i] = ~b[i];
default
b1 = {(WORDSIZE+1){1'bx}};
endcase
for (i=0; i<WORDSIZE; i=i+1)
begin
asb[i] = a1[i] ^ b1[i] ^ carry[i];
carry[i+1] = (a1[i]&b1[i]) |
(a1[i]&carry[i]) |
(b1[i]&carry[i]) ;
case (i)
'd 7 ,
'd 15 ,
'd 31 ,
'd 63 : stat[i] = carry[i+1];
default if (i == WORDSIZE-1)
stat[i] = carry[i+1];
else
stat[i] = 'b 0;
endcase
end
end
endfunction
assign #DELAY
SO = asb(A,B,INST_CIN,INST_SA,INST_SB),
INST_COUT = carry[WORDSIZE],
STATUS = stat;
endmodule