/**************************************************************/
/*    Verilog module of datapath cell DPBSH000H              */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      July, 1992              */
/*    Modified by    Linda J. Xu      Nov. 2, 1992            */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A    : the input port                               */
/*        B    : the input port                               */
/*        Z    : the output port                              */
/*    Control ports                                           */
/*        INST_S  : the select control signal                 */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        NUMBER_OF_SHIFTS  : the number of shift bits        */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpbsh000h(A, B, Z, INST_S);

  parameter WORDSIZE = 8, NUMBER_OF_SHIFTS = 8, DELAY = 5, BF = 1;
  input  [WORDSIZE-1:0] A, B;
  output [WORDSIZE-1:0] Z;
  input  [NUMBER_OF_SHIFTS:0] INST_S;

  reg [2*WORDSIZE-1:0] ZZ;


  function [WORDSIZE-1:0] bsh;
    input [WORDSIZE-1:0] A, B;
    input [NUMBER_OF_SHIFTS:0] S;

    integer i, shift, num_1;

    begin
      i = 0;
      shift = 0;
      num_1 = 0;

      while (i<NUMBER_OF_SHIFTS + 1)
        begin
          case (S[i])
            'b1:  num_1 = num_1 + 1;
            'b0:  if (num_1 < 1) shift = shift + 1;
            default
                begin
                  i = NUMBER_OF_SHIFTS + 1;
                  num_1 = 2;
                end
          endcase
          i = i + 1;
        end

      if (num_1 < 1)
        begin
          bsh = ZZ[WORDSIZE-1:0];
        end
      else if (num_1 > 1)
        begin
          bsh = {WORDSIZE{1'b x}};
        end
      else
        begin
          ZZ = ({B,A} >> shift);
          bsh = ZZ[WORDSIZE-1:0];
        end
    end
  endfunction

    assign #DELAY Z = bsh(A, B, INST_S);

endmodule