dpbsh005h.vmd
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/**************************************************************/
/* Verilog module of datapath cell DPBSH005H */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* B : the input port */
/* SEL : the input port */
/* Z : the output port */
/* Control ports */
/* INST_S : the switch A/B control signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* NUMBER_OF_SHIFTS : the number of shift bits */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpbsh005h(A, B, SEL, Z, INST_S);
parameter WORDSIZE = 8, NUMBER_OF_SHIFTS = 8, DELAY = 5, BF = 1;
input [WORDSIZE-1:0] A, B, SEL;
output [WORDSIZE-1:0] Z;
input INST_S;
reg [2*WORDSIZE-1:0] ZZ;
reg [NUMBER_OF_SHIFTS-1:0] ZZZ;
function [WORDSIZE-1:0] bsh;
input [WORDSIZE-1:0] A, B, SEL;
input switch;
integer i, shift, num_1, size;
begin
i = WORDSIZE;
shift = 0;
num_1 = 0;
if (WORDSIZE > NUMBER_OF_SHIFTS)
size = WORDSIZE - NUMBER_OF_SHIFTS - 1;
else if (WORDSIZE == NUMBER_OF_SHIFTS)
size = 0;
while (i>size)
begin
i = i - 1;
case (SEL[i])
'b1: num_1 = num_1 + 1;
'b0: if (num_1 < 1) shift = shift + 1;
default
begin
i = 0;
num_1 = 2;
end
endcase
end
if (WORDSIZE == NUMBER_OF_SHIFTS)
case (switch)
'b1: num_1 = num_1 + 1;
'b0: ;
default num_1 = 2;
endcase
if (num_1 < 1)
begin
bsh = ZZ[2*WORDSIZE-1:WORDSIZE];
end
else if (num_1 > 1)
begin
bsh = {WORDSIZE{1'b x}};
end
else
begin
if (WORDSIZE == NUMBER_OF_SHIFTS)
ZZ = ({A,B} << shift);
else if (WORDSIZE > NUMBER_OF_SHIFTS)
begin
ZZZ = B[NUMBER_OF_SHIFTS - 1 : 0];
ZZ = {A, ZZZ, {(WORDSIZE-NUMBER_OF_SHIFTS){1'b0}}} << shift;
end
else
begin
bsh = {WORDSIZE{1'b x}};
end
bsh = ZZ[2*WORDSIZE-1:WORDSIZE];
end
end
endfunction
assign #DELAY Z = bsh(A, B, SEL, INST_S);
endmodule