/**************************************************************/
/*    Verilog module of datapath cell DPCLKCKF0               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      July, 1992              */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        CLK   : the input port                              */
/*        CN    : the output port                             */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkckf0(CLK, CN);

  parameter DELAY = 3;
  input  CLK;
  output CN;
  wire   #DELAY CN = ~CLK;

endmodule