/**************************************************************/
/*    Verilog module of datapath cell DPCLKCLO0               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      Feb. 04, 1993           */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        CLK   : the input port                              */
/*        C     : the output port                             */
/*        CN    : the output port                             */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkclo0(CLK, C, CN);

  parameter DELAY = 3;
  input  CLK;
  output C, CN;
  wire   #DELAY C = ~(~CLK), CN = ~CLK;

endmodule