/**************************************************************/
/*    Verilog module of datapath cell dpclkglo0               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      Compass     Feb. 04, 93 */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        INST     : the input port                          */
/*        Z        : the output port                         */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkglo0(INST, Z);

  parameter DELAY = 3, BF = 1;
  input  INST;
  output Z;
  wire   #DELAY Z = ~(~INST);

endmodule