/**************************************************************/
/*    Verilog module of datapath cell dpclkobt0              */
/*    Designed by    Chunling Liu   Compass       Aug. 4, 92  */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        INST_CON    : the input port                          */
/*        Z  : the output port                         */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkobt0(INST_CON, Z);

  parameter DELAY = 3, BF = 1;
  input INST_CON;
  output Z;
  wire   #DELAY Z = ~(~INST_CON);

endmodule