/**************************************************************/
/*    Verilog module of datapath cell DPCLKTGC0               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      July, 1992              */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        E   : the input port                                */
/*        CLK : the input port                                */
/*        C   : the output port                               */
/*    Parameters                                              */
/*        WORDSIZE   : the word size of the datapath cell      */
/*        TYP      : the type of gated clock buffer          */
/*                    0 for False; 1 for True                 */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclktgc0(E, CLK, C);

  parameter WORDSIZE = 1, TYP = 1, DELAY = 3;
  input  [WORDSIZE-1:0] E;
  input  CLK;
  output [WORDSIZE-1:0] C;
  wire   [WORDSIZE-1:0] #DELAY C = (TYP) ?
                          E & {WORDSIZE{CLK}}:
                          ~(E & {WORDSIZE{CLK}});

endmodule