dpcmp000s.vmd
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/**************************************************************/
/* Verilog module of datapath cell DPCMP000S */
/* Designed by Lin Yang VLSI Technology Feb. 01, 91 */
/* Designed by Linda J. Xu Compass Oct, 27, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* B : the input port */
/* Control ports */
/* INST_AGB : the control output for A > B */
/* INST_EQ : the control output for A = B */
/* INST_AGBI : the optional cascade input for A > B */
/* INST_EQI : the optional cascade input for A = B */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* twos_complement : the unsigned/2's */
/* complement option */
/* cascade_inputs : the cascade inputs option */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpcmp000s(A, B, INST_AGB, INST_EQ, INST_AGBI, INST_EQI);
parameter WORDSIZE = 8, twos_complement = 1,
cascade_inputs = 1, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] A, B;
output INST_AGB, INST_EQ;
input INST_AGBI, INST_EQI;
wire INST_AGBI, INST_EQI;
function [1:0] cmp;
input [WORDSIZE-1:0] a, b;
input agbi, eqi;
reg [WORDSIZE-1:0] aa, ab;
reg [1:0] z;
begin
if (twos_complement == 1)
begin
aa = {~a[WORDSIZE-1], a[WORDSIZE-2:0]};
ab = {~b[WORDSIZE-1], b[WORDSIZE-2:0]};
end
else
begin
aa = a; ab = b;
end
if (aa == ab)
begin
if (cascade_inputs == 1)
z = {agbi, eqi};
else
z = 2'b01;
end
else if (aa < ab)
z = 2'b00;
else if (aa > ab)
z = 2'b10;
else
z = 2'bxx;
if (BF == 0)
begin
if (cascade_inputs == 0)
begin
if (((WORDSIZE >= 5) & (WORDSIZE <= 8)) |
((WORDSIZE >= 17) & (WORDSIZE <= 32)) |
((WORDSIZE >= 65) & (WORDSIZE <= 128)))
z = ~z;
end
else
if (((WORDSIZE >= 4) & (WORDSIZE <= 7)) |
((WORDSIZE >= 16) & (WORDSIZE <= 31)) |
((WORDSIZE >= 64) & (WORDSIZE <= 127)))
z = ~z;
end
cmp = z;
end
endfunction
assign #DELAY {INST_AGB, INST_EQ} = cmp(A, B, INST_AGBI, INST_EQI);
endmodule