/**************************************************************/
/*    Verilog module of datapath cell dpcsa010h               */
/*    Designed by    Chunling Liu Compass         June 08 1992*/
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A1     : the input port                             */
/*        A2     : the input port                             */
/*        A3     : the input port                             */
/*        S1     : the output port                            */
/*        S2     : the output port                            */
/*    Control ports                                           */
/*        INST_CIN  : the carry input                         */
/*        INST_COUT : the carry output                        */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpcsa010h(A1, A2, A3, S1, S2, INST_CIN, INST_COUT);

  parameter WORDSIZE = 8, DELAY = 15, BF = 1;
  input  [WORDSIZE-1:0] A1, A2, A3;
  output [WORDSIZE-1:0] S1, S2;
  input  INST_CIN;
  output INST_COUT;

  assign #DELAY
     S2 = A1 ^ A2 ^ A3,
     {INST_COUT,S1} = {((A1&A2) | (A2&A3) | (A1&A3)),INST_CIN};

endmodule