dpddl000h.vmd
2.53 KB
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/**************************************************************/
/* Verilog module of datapath cell dpddl000h */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu Compass Nov. 23, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* IN : the input port */
/* OUT : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* CDN : the active-low clear signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* */
/* When the clock signal changes from unknown to 1 or */
/* from 0 to unknown while the clear signal is high, */
/* the output will be unknown. */
/**************************************************************/
module dpddl000h(IN, OUT, INST_CP, CDN);
parameter WORDSIZE = 8, Number_of_delays = 2, DELAY = 10, BF = 1;
input [WORDSIZE-1:0] IN;
output [WORDSIZE-1:0] OUT;
input INST_CP, CDN;
reg [WORDSIZE-1:0] OUT;
reg [WORDSIZE-1:0] rgf[Number_of_delays-1:0];
reg flag;
initial OUT = {WORDSIZE{1'bx}};
initial flag = 1'b0;
function [WORDSIZE-1:0] dff;
input [WORDSIZE-1:0] d;
integer i;
begin
if (!CDN)
for (i = 0; i< Number_of_delays; i=i+1)
begin
rgf[i] = {WORDSIZE{1'b0}};
end
else if (CDN)
begin
for (i = Number_of_delays-1; i>= 1; i=i-1)
begin
rgf[i] = rgf[i-1];
end
rgf[0] = d;
end
dff = rgf[Number_of_delays-1];
end
endfunction
always @CDN
if (!CDN)
assign OUT = {WORDSIZE{1'b0}};
else if (CDN)
deassign OUT;
else
assign OUT = {WORDSIZE{1'b x}};
always @ (posedge INST_CP)
if ((INST_CP === 1'b1) && (flag === 1'b0))
OUT = #DELAY dff(IN);
else
begin
OUT = {WORDSIZE{1'b x}};
flag = 1'b1;
end
always @ (negedge INST_CP)
if (INST_CP === 1'b0)
flag = 1'b0;
else
flag = 1'b1;
endmodule