/**************************************************************/
/*    Verilog module of datapath cell DPDEC000H               */
/*    Designed by    Lin Yang    VLSI Technology  Nov. 5, 90  */
/*    Designed by    Linda J. Xu      August, 1992            */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A    : the input port                               */
/*        Z    : the output port                              */
/*    Control ports                                           */
/*        INST_CIN  : the carry input                         */
/*        INST_COUT : the carry output                        */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpdec000h(A, Z, INST_CIN, INST_COUT);

  parameter WORDSIZE = 8, DELAY = 15, BF = 1;
  input  [WORDSIZE-1:0] A;
  output [WORDSIZE-1:0] Z;
  input  INST_CIN;
  output INST_COUT;

  reg [WORDSIZE:0] carry;
  reg odd;

  function [WORDSIZE-1:0] dec;
     input [WORDSIZE-1:0] a;
     input cin;

     integer i;

     begin
       odd = WORDSIZE;
       carry[0] = cin;
       for (i=0; i<WORDSIZE; i=i+1)
         begin
            dec[i]  = a[i] ^ carry[i];
            carry[i+1]  =  ~a[i]&carry[i];
         end
     end
  endfunction

  assign #DELAY
     INST_COUT = ((BF == 0) & odd) ?
                 ~carry[WORDSIZE] : carry[WORDSIZE],
     Z = dec(A,INST_CIN);

endmodule