dpdff0501.vmd
2.23 KB
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/**************************************************************/
/* Verilog module of datapath cell dpdff0501 */
/* Designed by Linda J. Xu Compass Nov. 23, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* D0 : the input port */
/* D1 : the input port */
/* D2 : the input port */
/* Q : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST : the select signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* */
/* When the clock signal changes from unknown to 1 or */
/* from 0 to unknown, the output will be unknown. */
/**************************************************************/
module dpdff0501(D0, D1, D2, Q, INST_CP, INST);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] D0, D1, D2;
output [WORDSIZE-1:0] Q;
input INST_CP;
input [2:0] INST;
reg [WORDSIZE-1:0] Q;
reg flag;
initial Q = {WORDSIZE{1'bx}};
initial flag = 1'b0;
function [WORDSIZE-1:0] dff;
input [WORDSIZE-1:0] d0, d1, d2;
begin
case (INST)
3'b 001 : dff = ~(~d0);
3'b 010 : dff = ~(~d1);
3'b 100 : dff = ~(~d2);
default dff = d0 & {WORDSIZE{INST[0]}} |
d1 & {WORDSIZE{INST[1]}} |
d2 & {WORDSIZE{INST[2]}};
endcase
end
endfunction
always @ ( posedge INST_CP )
if ((INST_CP === 1'b1) && (flag === 1'b0))
Q = #DELAY dff(D0, D1, D2);
else
begin
Q = {WORDSIZE{1'b x}};
flag = 1'b1;
end
always @ (negedge INST_CP)
if (INST_CP === 1'b0)
flag = 1'b0;
else
flag = 1'b1;
endmodule