/**************************************************************/
/*    Verilog module of datapath cell dpdff0601              */
/*    Designed by  Linda J. Xu     Compass    Nov. 23, 1992   */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        D    : the input port                               */
/*        Q    : the output port                              */
/*    Control ports                                           */
/*        INST_CP    : the clock signal                       */
/*        INST_CLR   : the clear signal                       */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*                                                            */
/*    When the clock signal changes from unknown to 1 or      */
/*        from 0 to unknown while the clear signal is low,    */
/*        the output will be unknown.                         */
/**************************************************************/
module dpdff0601(D, Q, INST_CP, INST_CLR);

  parameter WORDSIZE = 8, DELAY = 3, BF = 1;
  input  [WORDSIZE-1:0] D;
  output [WORDSIZE-1:0] Q;
  input  INST_CP, INST_CLR;

  reg    [WORDSIZE-1:0] Q;
  reg    flag;

  initial Q = {WORDSIZE{1'bx}};
  initial flag = 1'b0;

  always @INST_CLR
        if (INST_CLR)
          assign Q = {WORDSIZE{1'b0}};
        else if (!INST_CLR)
          deassign Q;
        else
          assign Q = {WORDSIZE{1'b x}};


  always @ (posedge INST_CP)
    if ((INST_CP === 1'b1) && (flag === 1'b0))
      Q = #DELAY ~(~D);
    else
      begin
        Q = {WORDSIZE{1'b x}};
        flag = 1'b1;
      end

  always @ (negedge INST_CP)
    if (INST_CP === 1'b0 )
      flag = 1'b0;
    else
      flag = 1'b1;


endmodule