dpdff0701.vmd
2.03 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
/**************************************************************/
/* Verilog module of datapath cell dpdff0701 */
/* Designed by Linda J. Xu Compass Nov. 23, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* Q : the output port */
/* QN : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST_CLR : the clear signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* */
/* When the clock signal changes from unknown to 1 or */
/* from 0 to unknown while the clear signal is low, */
/* the output will be unknown. */
/**************************************************************/
module dpdff0701(D, Q, QN, INST_CP, INST_CLR);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] D;
output [WORDSIZE-1:0] Q, QN;
input INST_CP, INST_CLR;
reg [WORDSIZE-1:0] Q;
reg flag;
initial Q = {WORDSIZE{1'bx}};
initial flag = 1'b0;
always @INST_CLR
if (INST_CLR)
assign Q = {WORDSIZE{1'b0}};
else if (!INST_CLR)
deassign Q;
else
assign Q = {WORDSIZE{1'b x}};
always @ (posedge INST_CP)
if ((INST_CP === 1'b1) && (flag === 1'b0))
Q = #DELAY ~(~D);
else
begin
Q = {WORDSIZE{1'b x}};
flag = 1'b1;
end
always @ (negedge INST_CP)
if (INST_CP === 1'b0)
flag = 1'b0;
else
flag = 1'b1;
assign QN = ~Q;
endmodule