dpdff0901.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpdff0901 */
/* Designed by Linda J. Xu Compass Nov. 23, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* Q : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST : load enable */
/* INST_INIT : initialization control input */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* */
/* When the clock signal changes from unknown to 1 or */
/* from 0 to unknown while the initialization signal */
/* is high and load enable is high, the output will */
/* be unknown. */
/**************************************************************/
module dpdff0901(D, Q, INST, INST_CP, INST_INIT);
parameter WORDSIZE = 8, initial_value = 'b00000000, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] D;
output [WORDSIZE-1:0] Q;
input INST_CP, INST_INIT, INST;
reg [WORDSIZE-1:0] Q;
reg flag;
initial Q = {WORDSIZE{1'bx}};
initial flag = 1'b0;
always @ (INST_INIT)
if (!INST_INIT)
assign Q = initial_value;
else if (INST_INIT)
deassign Q;
else
assign Q = {WORDSIZE{1'b x}};
always @ INST
if (INST_INIT)
begin
if (!INST)
assign Q = ~(~Q);
else
deassign Q;
end
always @ ( posedge INST_CP )
if ((INST_CP === 1'b1) && (flag === 1'b0))
Q = #DELAY ~(~D);
else
begin
Q = {WORDSIZE{1'b x}};
flag = 1'b1;
end
always @ (negedge INST_CP)
if (INST_CP === 1'b0)
flag = 1'b0;
else
flag = 1'b1;
endmodule