dpdff1001.vmd
2.46 KB
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/**************************************************************/
/* Verilog module of datapath cell dpdff1001 */
/* Designed by Linda J. Xu Compass Nov. 23, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* Q : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST_SCEN : load enable */
/* INST_INIT : initialization control input */
/* INST_SCOUT : initialization control output */
/* INST_SCCIN : initialization control input */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* When the clock signal changes from unknown to 1 or */
/* from 0 to unknown while the intialization signal */
/* is high, the output will be unknown. */
/**************************************************************/
module dpdff1001(D, Q, INST_SCOUT, INST_CP, INST_INIT, INST_SCEN, INST_SCIN);
parameter WORDSIZE = 8, initial_value = 'b00000000, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] D;
output [WORDSIZE-1:0] Q;
output INST_SCOUT;
input INST_SCIN, INST_SCEN;
input INST_CP, INST_INIT;
reg [WORDSIZE-1:0] Q;
reg INST_SCOUT;
reg flag;
initial begin
Q = {WORDSIZE{1'bx}};
INST_SCOUT = 'bx;
flag = 1'b0;
end
always @ ( INST_INIT )
if ( !INST_INIT )
assign Q = initial_value;
else if (INST_INIT)
deassign Q;
else
assign Q = {WORDSIZE{1'bx}};
always @ (posedge INST_CP)
if ((INST_CP === 1'b1) && (flag === 1'b0))
begin
if (INST_SCEN)
Q = #DELAY {Q[WORDSIZE-2: 0], INST_SCIN};
else if (!INST_SCEN)
Q = #DELAY ~(~D);
else
Q = {WORDSIZE{1'b x}};
end
else
begin
Q = {WORDSIZE{1'b x}};
flag = 1'b1;
end
always @ (negedge INST_CP)
if (INST_CP === 1'b0)
flag = 1'b0;
else
flag = 1'b1;
always @ (Q) INST_SCOUT = #1 ~(~Q[WORDSIZE-1]);
endmodule