dpdff1111.vmd
2.21 KB
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/**************************************************************/
/* Verilog module of datapath cell dpdff1111 */
/* Designed by Chunling Liu Compass Aug. 4, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* Z : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* OE : load enable */
/* INST_INIT : initialization control input */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpdff1111(D, Z, INST_CP, INST_INIT, OE);
parameter WORDSIZE = 8, initial_value = 'b00000000, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] D, OE;
output [WORDSIZE-1:0] Z;
input INST_CP, INST_INIT;
integer i;
reg [WORDSIZE-1:0] Z;
function [WORDSIZE:0] tsbt;
input [WORDSIZE-1:0] in;
input [WORDSIZE-1:0] oe;
integer i;
begin
for (i=0; i<WORDSIZE; i=i+1)
case (oe[i])
'b1 : tsbt[i] = ~(~in[i]);
'b0 : tsbt[i] = 'b z;
default tsbt[i] = 'b x;
endcase
end
endfunction
function [WORDSIZE:0] tsbf;
input [WORDSIZE-1:0] in;
input [WORDSIZE-1:0] oe;
integer i;
begin
for (i=0; i<WORDSIZE; i=i+1)
case (oe[i])
'b1 : tsbf[i] = ~(~in[i]);
'b0 : tsbf[i] = 'b z;
default tsbf[i] = 'b x;
endcase
end
endfunction
initial Z = {WORDSIZE{1'bx}};
always @ ( posedge INST_CP )
Z = #DELAY ~(~D);
always @ ( INST_INIT )
if ( !INST_INIT )
#DELAY assign Z = tsbf(initial_value, OE);
else
#DELAY deassign Z;
always @ ( OE )
Z = tsbt(D, OE);
endmodule