dpibt1121.vmd
1.52 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
/**************************************************************/
/* Verilog module of datapath cell dpibt1121 */
/* Designed by Lin Yang VLSI Technology Oct. 30, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I : the input port */
/* ZN : the output port */
/* OE : the bitwise output enable signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpibt1121(I, ZN, OE);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] I;
output [WORDSIZE-1:0] ZN;
input [WORDSIZE-1:0] OE;
function [WORDSIZE:0] ibt;
input [WORDSIZE-1:0] in;
input [WORDSIZE-1:0] oe;
integer i;
begin
for (i=0; i<WORDSIZE; i=i+1)
case (oe[i])
'b1 : ibt[i] = ~in[i];
'b0 : ibt[i] = 'b z;
default ibt[i] = 'b x;
endcase
end
endfunction
assign #DELAY ZN = ibt(I, OE);
endmodule