/**************************************************************/
/*    Verilog module of datapath cell dplat0001              */
/*    Designed by    Chunling Liu  Compass        Aug. 4, 92  */
/*    Changed  by    Matt Rohm     SGI            May 27, 94  */
/*    (fixed the DELAY assigments)                            */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        D    : the input port                               */
/*        Q    : the output port                              */
/*    Control ports                                           */
/*        INST_CP    : the clock signal                       */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dplat0001(D, Q, INST_CP);

  parameter WORDSIZE = 8, DELAY = 4, BF = 1;
  input  [WORDSIZE-1:0] D;
  output [WORDSIZE-1:0] Q;
  input  INST_CP;

  reg    [WORDSIZE-1:0] Q;

  initial Q = {WORDSIZE{1'bx}};

  function [WORDSIZE-1:0] lat;
  input  [WORDSIZE-1:0] d;
  integer i;

    begin
      case (INST_CP)
        'b 0 : lat = Q;
        'b 1 : lat = ~(~d);
        default lat = {WORDSIZE{1'b x}};
      endcase
    end
  endfunction

  always @ (INST_CP or D)  Q = #DELAY lat(D);

endmodule