/**************************************************************/
/*    Verilog module of datapath cell DPLOD000s               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu   Compass       Oct. 27,  92 */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        IN   : the input port                               */
/*        OUT  : the output port                              */
/*    Control ports                                           */
/*        INST_ZERO  : the zero detect flag                   */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        ALL_ZERO_OK  : the flag for the all zero input case    */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dplod000s(IN, OUT, INST_ZERO);

  parameter WORDSIZE = 8, ALL_ZERO_OK = 0, DELAY = 4, BF = 1;
  input  [WORDSIZE-1:0] IN;
  output [WORDSIZE-1:0] OUT;
  output INST_ZERO;

  function [WORDSIZE:0] lod;
    input [WORDSIZE-1:0] X;

    integer i, counter;

    begin
      i = WORDSIZE;
      counter = 0;
      lod = {WORDSIZE+1{1'b0}};

      while (i>0)
        begin
          i = i - 1;
          case (X[i])
            'b1:
                begin
                  lod[i] = 'b 1;
                  i = 0;
                end
            'b0:  counter = counter + 1;
            default
                begin
                  lod = {WORDSIZE+1{1'bx}};
                  i = 0;
                end
          endcase
        end

      if (counter == WORDSIZE)
      begin
          lod[WORDSIZE] = 'b 1;
          if (ALL_ZERO_OK == 0)
            lod[WORDSIZE-1] = 'b 1;
      end
    end
  endfunction

  assign #DELAY {INST_ZERO, OUT} = lod(IN);

endmodule