dpmlt011h.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpmlt011h.v */
/* Designed by Lin Yang VLSI Technology Jan. 30, 91 */
/* Designed by Chunling Liu Compass June 29 92 */
/* Designed by Linda J. Xu Compass August, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* Y : the input port */
/* MSB0 : the output port */
/* MSB1 : the output port */
/* LSB : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Y_bus_size : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpmlt011h(X, Y, MSB0, MSB1, LSB);
parameter WORDSIZE = 8, Y_bus_size = 8, DELAY = 30, BF = 1;
input [WORDSIZE-1:0] X, Y;
output [WORDSIZE-1:0] MSB0, MSB1, LSB;
function [2*WORDSIZE-1:0] mlt;
input [WORDSIZE-1:0] x;
input [Y_bus_size-1:0] y;
reg [WORDSIZE+Y_bus_size-1:0] a;
reg [WORDSIZE-1:0] sx;
reg [Y_bus_size-1:0] sy;
begin
if (x[WORDSIZE-1]^y[Y_bus_size-1])
begin
if (x[WORDSIZE-1] == 1)
begin
sx = ~x + 1;
sy = y;
end
else if (y[Y_bus_size-1] == 1)
begin
sx = x;
sy = ~y + 1;
end
a = ~(sx * sy) + 1;
end
else if (x[WORDSIZE-1]^~ y[Y_bus_size-1])
begin
if(x[WORDSIZE-1])
begin
sx = ~x + 1;
sy = ~y + 1;
end
else
begin
sx = x;
sy = y;
end
a = sx * sy;
end
else
a = {WORDSIZE+Y_bus_size{1'bx}};
mlt[WORDSIZE-1:0] = {{WORDSIZE-Y_bus_size{1'b0}},a[Y_bus_size-1:0]};
mlt[2*WORDSIZE-1:WORDSIZE] = a[WORDSIZE+Y_bus_size-1:Y_bus_size];
end
endfunction
assign #DELAY {MSB1, LSB} = mlt(X,Y),
MSB0 = 0;
endmodule