dpmlt022m.vmd
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/**************************************************************/
/* Verilog module of datapath cell DPMLT022M */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Chunling Liu Compass June 12, 92 */
/* Designed by Linda J. Xu Compass Dec. 11, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* Y : the input port */
/* MSB : the output port */
/* LSB : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Number_Of_Words : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpmlt022m(X, Y, MSB, LSB, INST_CP);
parameter WORDSIZE = 8, Number_Of_Words = 8, DELAY = 30, BF = 1;
input [WORDSIZE-1:0] X, Y;
output [WORDSIZE-1:0] MSB, LSB;
input INST_CP;
reg [WORDSIZE-1:0] MSB, LSB;
reg [2*WORDSIZE-1:0] tmp;
function [2*WORDSIZE-1:0] mlt;
input [WORDSIZE-1:0] x;
input [WORDSIZE-1:0] y;
reg [WORDSIZE+Number_Of_Words-1:0] z;
reg [Number_Of_Words-1:0] y1;
integer i;
begin
y1 = y[Number_Of_Words-1:0];
z = x * y1;
// mlt[WORDSIZE-1:0] = {{WORDSIZE-Number_Of_Words{1'b0}}, z[Number_Of_Words-1:0]};
if (WORDSIZE > Number_Of_Words)
begin
for (i = Number_Of_Words; i < WORDSIZE; i = i+1)
mlt[i] = y[i];
mlt[Number_Of_Words-1:0] = z[Number_Of_Words-1:0];
end
else
mlt[WORDSIZE-1:0] = z[WORDSIZE-1:0];
mlt[2*WORDSIZE-1:WORDSIZE] = z[WORDSIZE+Number_Of_Words-1:Number_Of_Words];
end
endfunction
initial MSB = {WORDSIZE{1'bx}};
always @(X or Y)
begin
tmp = #DELAY mlt(X,Y);
LSB = tmp[WORDSIZE-1:0];
end
always @(posedge INST_CP)
MSB = #DELAY tmp[2*WORDSIZE-1:WORDSIZE];
endmodule