dpmux0121.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpmux0121 */
/* Designed by Lin Yang VLSI Technology Nov. 5, 90 */
/* Designed by Linda J. Xu August, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I0 : the input port */
/* I1 : the input port */
/* Z : the output port */
/* SD : the select input */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpmux0121(I0, I1, Z, SD);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] I0, I1;
output [WORDSIZE-1:0] Z;
input [WORDSIZE-1:0] SD;
function [WORDSIZE-1:0] mux;
input [WORDSIZE-1:0] i0, i1;
input [WORDSIZE-1:0] sel;
integer i;
begin
for (i=0; i<WORDSIZE; i=i+1)
case (sel[i])
1'b 0 : mux[i] = ~(~i0[i]);
1'b 1 : mux[i] = ~(~i1[i]);
default mux[i] = 1'b x;
endcase
end
endfunction
assign #DELAY Z = mux(I0, I1, SD);
endmodule