dpmux2021.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpmux2021 */
/* Designed by Lin Yang VLSI Technology Nov. 2, 90 */
/* Designed by Linda J. Xu August, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I0 : the input port */
/* I1 : the input port */
/* Z : the output port */
/* Control ports */
/* INST : the select input signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpmux2021(I0, I1, Z, INST);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] I0, I1;
output [WORDSIZE-1:0] Z;
input [1:0] INST;
function [WORDSIZE-1:0] mux;
input [WORDSIZE-1:0] i0, i1;
input [1:0]sel;
begin
case (sel)
2'b 00 : mux = {WORDSIZE{1'b 0}};
2'b 01 : mux = ~(~i0);
2'b 10 : mux = ~(~i1);
2'b 11 : mux = (i0|i1);
default mux = {WORDSIZE{1'b x}};
endcase
end
endfunction
assign #DELAY Z = mux(I0, I1, INST);
endmodule