dpmux2041.vmd
1.7 KB
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/**************************************************************/
/* Verilog module of datapath cell dpmux2041 */
/* Designed by Chunling liu Compass July 20, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* I0 : the input port */
/* I1 : the input port */
/* I2 : the input port */
/* I3 : the input port */
/* Z : the output port */
/* Control ports */
/* INST_S0 : the select input signal */
/* INST_S1 : the select input signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpmux2041(I0, I1, I2, I3, ZN, INST_S1, INST_S0);
parameter WORDSIZE = 8, DELAY = 4;
input [WORDSIZE-1:0] I0, I1, I2, I3;
output [WORDSIZE-1:0] ZN;
input INST_S1, INST_S0;
function [WORDSIZE-1:0] mux;
input [WORDSIZE-1:0] i0, i1, i2, i3;
input [1:0]sel;
begin
case (sel)
2'b 00 : mux = ~i0;
2'b 01 : mux = ~i1;
2'b 10 : mux = ~i2;
2'b 11 : mux = ~i3;
default mux = {WORDSIZE{1'b x}};
endcase
end
endfunction
assign #DELAY ZN = mux(I0, I1, I2, I3, {INST_S1,INST_S0});
endmodule