dpmux3031.vmd
1.72 KB
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/**************************************************************/
/* Verilog module of datapath cell dpmux3031 */
/* Designed by Lin Yang VLSI Technology Nov. 2, 90 */
/* Designed by Linda J. Xu August, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I0 : the input port */
/* I1 : the input port */
/* I2 : the input port */
/* Z : the output port */
/* Control ports */
/* INST : the select input signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpmux3031(I0, I1, I2, Z, INST);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] I0, I1, I2;
output [WORDSIZE-1:0] Z;
input [2:0] INST;
function [WORDSIZE-1:0] mux;
input [WORDSIZE-1:0] i0, i1, i2;
input [2:0] sel;
integer i;
begin
i = 0;
while (i < WORDSIZE)
begin
mux[i] = (sel[0] & i0[i]) | (sel[1] & i1[i]) | (sel[2] & i2[i]);
i = i + 1;
end
end
endfunction
assign #DELAY Z = mux(I0, I1, I2, INST);
endmodule