dpmux8081.vmd
2.26 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
/**************************************************************/
/* Verilog module of datapath cell dpmux8081 */
/* Designed by Lin Yang VLSI Technology Nov. 2, 90 */
/* Designed by Linda J. Xu August, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I0 : the input port */
/* I1 : the input port */
/* I2 : the input port */
/* I3 : the input port */
/* I4 : the input port */
/* I5 : the input port */
/* I6 : the input port */
/* I7 : the input port */
/* Z : the output port */
/* Control ports */
/* INST : the select input signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpmux8081(I0, I1, I2, I3, I4, I5, I6, I7, Z, INST);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] I0, I1, I2, I3, I4, I5, I6, I7;
output [WORDSIZE-1:0] Z;
input [7:0] INST;
function [WORDSIZE-1:0] mux;
input [WORDSIZE-1:0] i0, i1, i2, i3, i4, i5, i6, i7;
input [7:0] sel;
integer i;
begin
i = 0;
while (i < WORDSIZE)
begin
mux[i] = (sel[0] & i0[i]) | (sel[1] & i1[i])
| (sel[2] & i2[i]) | (sel[3] & i3[i])
| (sel[4] & i4[i]) | (sel[5] & i5[i])
| (sel[6] & i6[i]) | (sel[7] & i7[i]);
i = i + 1;
end
end
endfunction
assign #DELAY Z = mux(I0, I1, I2, I3, I4, I5, I6, I7, INST);
endmodule