/**************************************************************/
/*    Verilog module of datapath cell DPNND0041               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      July, 1992              */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A1   : the input port                               */
/*        A2   : the input port                               */
/*        A3   : the input port                               */
/*        A4   : the input port                               */
/*        ZN   : the output port                              */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpnnd0041(A1, A2, A3, A4, ZN);

  parameter WORDSIZE = 8, DELAY = 1, BF = 1;
  input  [WORDSIZE-1:0] A1, A2, A3, A4;
  output [WORDSIZE-1:0] ZN;
  wire   [WORDSIZE-1:0] #DELAY ZN = ~(A1 & A2 & A3 & A4);

endmodule