dpnnd1021.vmd
1.42 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
/**************************************************************/
/* Verilog module of datapath cell DPNND1021 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A1 : the input port */
/* INST : the control input port */
/* ZN : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpnnd1021(A1, INST, ZN);
parameter WORDSIZE = 8, DELAY = 1, BF = 1;
input [WORDSIZE-1:0] A1;
input INST;
output [WORDSIZE-1:0] ZN;
function [WORDSIZE-1:0] nnd;
input [WORDSIZE-1:0] A1;
input INST;
integer i;
begin
i = 0;
for (i = 0; i < WORDSIZE; i = i+1)
nnd[i] = ~(A1[i] & INST);
end
endfunction
assign #DELAY ZN = nnd (A1, INST);
endmodule