dppar000m.vmd
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/**************************************************************/
/* Verilog module of datapath cell DPPAP000M */
/* Designed by Lin Yang VLSI Technology Feb. 5, 91 */
/* Designed by Linda J. Xu Compass Oct. 27, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* Control ports */
/* INST_Z : the zero detect flag */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dppar000m(A, INST_Z);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] A;
output INST_Z;
function par;
input [WORDSIZE-1:0] X;
integer i, n, flag;
begin
n = 0;
flag = 0;
for (i=0; i<WORDSIZE; i=i+1)
if (X[i] == 1)
n = n + 1;
else if (X[i] != 0)
flag = 1;
if (flag == 1)
par = 1'bx;
else
par = n;
end
endfunction
assign #DELAY INST_Z = par(A);
endmodule