/**************************************************************/
/*    Verilog module of datapath cell DPPEC000S               */
/*    Designed by    Linda J. Xu      Feb. 10, 1992           */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        IN   : the input port                               */
/*    Control ports                                           */
/*        INST_B  : the encoded output                        */
/*        INST_ZERO  : the zero detect flag                   */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        LOG_OF_WORDSIZE  : the log value of word size       */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
//module dppec000s(IN, INST_B6, INST_B5, INST_B4, INST_B3,
//                  INST_B2, INST_B1, INST_B0, INST_ZERO);
module dppec000s(IN, INST_B, INST_ZERO);

  parameter WORDSIZE = 8, LOG_OF_WORDSIZE = 1, DELAY = 4, BF = 1;
  input  [WORDSIZE-1:0] IN;
//  output INST_B0, INST_B1, INST_B2, INST_B3, INST_B4, INST_B5, INST_B6;
  output [LOG_OF_WORDSIZE-1:0] INST_B;
  output INST_ZERO;

  function [LOG_OF_WORDSIZE:0] pec;
    input [WORDSIZE-1:0] X;

    integer i, counter;

    begin
      i = WORDSIZE;
      counter = 0;

      while (i>0)
        begin
          i = i - 1;
          case (X[i])
            'b1:  i = 0;
            'b0:  counter = counter + 1;
            default
                begin
                  i = 0;
                  counter = WORDSIZE + 1;
                end
          endcase
        end

      if (counter < WORDSIZE)
        begin
          pec = counter;
        end
      else if (counter == WORDSIZE)
        begin
          pec[LOG_OF_WORDSIZE-1:0] = {LOG_OF_WORDSIZE{1'b0}};
          pec[LOG_OF_WORDSIZE] = 1'b 1;
        end
      else
          pec = {(LOG_OF_WORDSIZE+1){1'bx}};
    end

  endfunction


  assign #DELAY {INST_ZERO, INST_B } = pec(IN);

endmodule