dprgf010h.vmd
3.93 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
/**************************************************************/
/* Verilog module of datapath cell dprgf010h */
/* Designed by Lin Yang VLSI Technology Nov. 7, 90 */
/* Modified by Linda J. Xu Compass Jan. 8, 94 */
/* (Changed port size INST_WL to [(NUMBER_of_WORDS+1)/2-1:0]*/
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* A : the output port */
/* B : the output port */
/* Control ports */
/* INST_WL : the low-order words write enable signal */
/* INST_WH : the high-order words write enable signal */
/* INST_RA : the read to port A select signal */
/* INST_RB : the read to port B select signal */
/* INST_SA : the word select signal for port A */
/* INST_SB : the word select signal for port B */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* NUMBER_of_WORDS : the column size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dprgf010h(D,A,B,INST_WL,INST_WH,INST_RA,INST_RB,INST_SA,INST_SB);
parameter WORDSIZE = 8, NUMBER_of_WORDS = 2, DELAY = 10, BF = 1;
input [WORDSIZE-1:0] D;
output [WORDSIZE-1:0] A, B;
input [(NUMBER_of_WORDS+1)/2-1:0] INST_WL, INST_WH, INST_RA, INST_RB;
input INST_SA, INST_SB;
reg [WORDSIZE-1:0] A, B;
reg [WORDSIZE-1:0] rgfl[(NUMBER_of_WORDS+1)/2-1:0], rgfh[(NUMBER_of_WORDS+1)/2-1:0];
reg dummy;
function write;
input [WORDSIZE-1:0] d;
input [(NUMBER_of_WORDS+1)/2-1:0] wl, wh;
integer i;
begin
for (i=0; i<(NUMBER_of_WORDS+1)/2; i=i+1)
begin
case (wl[i])
1'b 1 : rgfl[i] = ~(~d);
1'b 0 : ;
default rgfl[i] = {WORDSIZE{1'b x}};
endcase
case (wh[i])
1'b 1 : rgfh[i] = ~(~d);
1'b 0 : ;
default rgfl[i] = {WORDSIZE{1'b x}};
endcase
end
write = 1'b 0;
end
endfunction
function [2*WORDSIZE-1:0] read;
input [(NUMBER_of_WORDS+1)/2-1:0]ra, rb;
input sa, sb;
integer i, flaga, flagb, indexa, indexb;
begin
// determine the register file index
flaga = 0;
flagb = 0;
for (i=0; i<(NUMBER_of_WORDS+1)/2; i=i+1)
begin
case (ra[i])
1'b 1 :
begin
flaga = flaga + 1;
indexa = i;
end
1'b 0 : ;
default flaga = 2;
endcase
case (rb[i])
1'b 1 :
begin
flagb = flagb + 1;
indexb = i;
end
1'b 0 : ;
default flagb = 2;
endcase
end
// read port A
if (flaga==1)
case (sa)
1'b 0 : read[WORDSIZE-1:0] = rgfl[indexa];
1'b 1 : read[WORDSIZE-1:0] = rgfh[indexa];
default read[WORDSIZE-1:0] = {WORDSIZE{1'b x}};
endcase
else
read[WORDSIZE-1:0] = {WORDSIZE{1'b x}};
// read port B
if (flagb==1)
case (sb)
1'b 0 : read[2*WORDSIZE-1:WORDSIZE] = rgfl[indexb];
1'b 1 : read[2*WORDSIZE-1:WORDSIZE] = rgfh[indexb];
default read[2*WORDSIZE-1:WORDSIZE] = {WORDSIZE{1'b x}};
endcase
else
read[2*WORDSIZE-1:WORDSIZE] = {WORDSIZE{1'b x}};
end
endfunction
always @ (D or INST_WL or INST_WH )
#DELAY dummy = write(D, INST_WL, INST_WH);
always @ (D or INST_WL or INST_WH or INST_RA or INST_RB or INST_SA or INST_SB)
#DELAY {B, A} = read(INST_RA, INST_RB, INST_SA, INST_SB);
endmodule