/**************************************************************/
/*    Verilog module of datapath cell dprpt0010              */
/*    Designed by    Chunling Liu    Compass    Aug. 4, 92    */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        I    : the inout port                               */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dprpt0010(I);

  parameter WORDSIZE = 8, BF = 1;
  inout  [WORDSIZE-1:0] I;
  trireg  [WORDSIZE-1:0] I;

endmodule