dpshf000m.vmd
2.16 KB
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/**************************************************************/
/* Verilog module of datapath cell DPSHF000M */
/* Designed by Lin Yang VLSI Technology Nov. 5, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* Modified by Linda J. Xu Nov. 2, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I : the input port */
/* Z : the output port */
/* Control ports */
/* INST_DI : the data input MSB */
/* INST_UI : the data input LSB */
/* INST_DO : the data output LSB */
/* INST_UO : the data output MSB */
/* INST : the 2-bit select control signal */
/* control[1] and control[0] */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpshf000m(I, Z, INST_DI, INST_UI, INST_DO, INST_UO, INST);
parameter WORDSIZE = 8, DELAY = 5, BF = 1;
input [WORDSIZE-1:0] I;
output [WORDSIZE-1:0] Z;
input INST_DI, INST_UI;
output INST_DO, INST_UO;
input [1:0] INST;
function [WORDSIZE-1:0] shf;
input [WORDSIZE-1:0] I;
input di, ui;
input [1:0] shift;
begin
case (shift)
2'b10, 2'b00: shf = I;
2'b01: shf = {di, I[WORDSIZE-1:1]} ;
2'b11: shf = {I[WORDSIZE-2:0], ui};
default shf = {WORDSIZE{1'bx}};
endcase
end
endfunction
assign #DELAY
INST_DO = ~(~I[0]),
INST_UO = ~(~I[WORDSIZE-1]),
Z = ~(~shf(I, INST_DI, INST_UI, INST));
endmodule