dptsb1022.vmd
1.52 KB
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/**************************************************************/
/* Verilog module of datapath cell dptsb1022 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I : the input port */
/* Z : the output port */
/* Control ports */
/* INST : the output enable signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dptsb1022(I, Z, INST);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] I;
output [WORDSIZE-1:0] Z;
input INST;
function [WORDSIZE:0] tsb;
input [WORDSIZE-1:0] in;
input oe;
begin
case (oe)
'b1 : tsb = ~(~in);
'b0 : tsb = {WORDSIZE{1'b z}};
default tsb = {WORDSIZE{1'b x}};
endcase
end
endfunction
assign #DELAY Z = tsb(I, INST);
endmodule