dptsb1131.vmd
1.52 KB
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/**************************************************************/
/* Verilog module of datapath cell dptsb1131 */
/* Designed by Lin Yang VLSI Technology Oct. 30, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* I : the input port */
/* Z : the output port */
/* OEN : the bitwise output enable signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dptsb1131(I, Z, OEN);
parameter WORDSIZE = 8, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] I;
output [WORDSIZE-1:0] Z;
input [WORDSIZE-1:0] OEN;
function [WORDSIZE:0] tsb;
input [WORDSIZE-1:0] in;
input [WORDSIZE-1:0] oen;
integer i;
begin
for (i=0; i<WORDSIZE; i=i+1)
case (oen[i])
'b0 : tsb[i] = ~(~in[i]);
'b1 : tsb[i] = 'b z;
default tsb[i] = 'b x;
endcase
end
endfunction
assign #DELAY Z = tsb(I, OEN);
endmodule